公开(公告)号：US20160211174A1

公开(公告)日：2016-07-21

申请号：US15083484

申请日：2016-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

公开(公告)号：US09134604B2

公开(公告)日：2015-09-15

申请号：US14015885

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD

Inventor： Chih-Tsung Shih ,  Hsin-Chieh Yao ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Chung-Ju Lee ,  Anthony Yen

IPC: G03F1/24 ,  G03F1/52 ,  G03F1/54 ,  G03F1/58

CPC classification number: G03F1/58 ,  G03F1/24 ,  G03F1/52 ,  G03F1/54

Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.

Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。

公开(公告)号：US20150064611A1

公开(公告)日：2015-03-05

申请号：US14015885

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chih-Tsung Shih ,  Hsin-Chieh Yao ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Chung-Ju Lee ,  Anthony Yen

IPC: G03F1/58 ,  G03F1/52

CPC classification number: G03F1/58 ,  G03F1/24 ,  G03F1/52 ,  G03F1/54

Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.

Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚度的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。

公开(公告)号：US20150056813A1

公开(公告)日：2015-02-26

申请号：US14537406

申请日：2014-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

Abstract: The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer.

Abstract translation: 本公开涉及在半导体衬底上形成图案的方法。 在半导体衬底上形成一层或多层。 在一个或多个层上形成第一自组装单层（SAM）层，其中第一SAM层展现出第一SAM图案。 使用第一SAM层作为第一蚀刻掩模来图案化一个或多个层中的至少第一层，以在一个或多个层中的第一层中形成第一柱，然后移除第一SAM层。 在去除第一SAM层之后，在第一柱的侧壁部分形成第二自组装单层（SAM）层，其中第二SAM层表现出与第一SAM图案不同的第二SAM图案，其中第二SAM 材料组成与第一SAM层不同。