公开(公告)号：US20060158936A1

公开(公告)日：2006-07-20

申请号：US11374045

申请日：2006-03-14

Applicant: Hiroshi Nakamura ,  Kenichi Imamiya

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya

IPC: G11C16/04

CPC classification number: G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  H01L27/115

Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

公开(公告)号：US20060146607A1

公开(公告)日：2006-07-06

申请号：US11366110

申请日：2006-03-01

Applicant: Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

Inventor： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC: G11C16/04

CPC classification number: G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

Abstract: A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

公开(公告)号：US07057930B2

公开(公告)日：2006-06-06

申请号：US11005594

申请日：2004-12-06

Applicant: Hiroshi Nakamura

Inventor： Hiroshi Nakamura

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C2216/16

Abstract: There is provided a semiconductor memory device, which realizes rewriting of data in the memory cell by applying a potential difference between the gate and the source, or applying a potential difference between the gate and the drain, which is larger than the power supply voltage. This semiconductor memory device is provided with a source line potential control circuit configured to control the source line potential. The source line potential control circuit sets the source line potential at the time of the mode for programming “1” data in a plurality of blocks in one package to a level lower than at the normal data programming mode.

公开(公告)号：US20060098488A1

公开(公告)日：2006-05-11

申请号：US11313826

申请日：2005-12-22

Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

公开(公告)号：US20060084665A1

公开(公告)日：2006-04-20

申请号：US11230330

申请日：2005-09-20

Applicant: Motohide Satoh ,  Hisateru Aramaki ,  Hiroshi Nakamura ,  Masafumi Inoue ,  Hiroshi Kawakami ,  Hisashi Shinkai ,  Yuji Matsuzaki ,  Kazunobu Yamataka

Inventor： Motohide Satoh ,  Hisateru Aramaki ,  Hiroshi Nakamura ,  Masafumi Inoue ,  Hiroshi Kawakami ,  Hisashi Shinkai ,  Yuji Matsuzaki ,  Kazunobu Yamataka

IPC: A61K31/519 ,  C07D455/02 ,  A61K31/4745

CPC classification number: C07D471/04 ,  A61K31/4745 ,  A61K31/519 ,  C07D455/02

Abstract: A pharmaceutical agent having an anti-HIV action, particularly, a pharmaceutical agent having an integrase inhibitory action, is provided. The present invention relates to a quinolizinone compound represented by the following formula [I] wherein each symbol is as defined in the specification, a pharmaceutically acceptable salt thereof, and an anti-HIV agent containing same as an active ingredient. The compound of the present invention has an HIV integrase inhibitory action and is useful as an anti-HIV agent for the prophylaxis or therapy of AIDS. Moreover, by a combined use with other anti-HIV agents such as protease inhibitors, reverse transcriptase inhibitors and the like, the compounds can become a more effective anti-HIV agent. Since the compound has a high inhibitory activity specific for integrases, the compound can provide a safe pharmaceutical agent for human with a fewer side effects.

Abstract translation: 提供具有抗HIV作用的药剂，特别是具有整合酶抑制作用的药剂。 本发明涉及由下式[I]表示的喹嗪酮化合物，其中各符号如说明书中所定义，其药学上可接受的盐和含有作为活性成分的抗HIV剂。 本发明的化合物具有HIV整合酶抑制作用，可用作预防或治疗AIDS的抗HIV剂。 此外，通过与其它抗HIV剂如蛋白酶抑制剂，逆转录酶抑制剂等的组合使用，化合物可以成为更有效的抗HIV剂。 由于化合物对整合酶具有高的抑制活性，所以化合物可以为人体提供安全的药剂，副作用较少。

公开(公告)号：US07010302B1

公开(公告)日：2006-03-07

申请号：US09462295

申请日：1999-05-07

Applicant: Akihisa Nakajima ,  Hiroshi Nakamura ,  Teruki Niwa ,  Yukichi Saito ,  Tomoyuki Ohtani ,  Hideo Morita

Inventor： Akihisa Nakajima ,  Hiroshi Nakamura ,  Teruki Niwa ,  Yukichi Saito ,  Tomoyuki Ohtani ,  Hideo Morita

IPC: H04Q7/20

CPC classification number: H04L61/605 ,  H04L29/12066 ,  H04L29/1216 ,  H04L29/12801 ,  H04L29/12896 ,  H04L61/1511 ,  H04L61/157 ,  H04L61/6004 ,  H04W8/26 ,  H04W40/00 ,  H04W40/20 ,  H04W40/24 ,  H04W80/04

Abstract: An address structure in mobile communications network facilitating routing of a packet. At the initial position of the address, is located a prefix or the like indicating the type of the address structure, which indicates the present mobile communications network system, for example. At the next position, a location address (LA) is located characterizing the present invention. The location address is usually placed at the position of a subnetwork address. The location address (LA) is provided for each mobile switching system, and constitutes part of an IP address of a user using a mobile station under the control of the mobile switching system. At the final position, is located a user identifier (user ID) which is used for identifying a user, and is provided uniquely for each user. The IP address in accordance with the present invention can be split into the foregoing three sections, part of which includes the location address and user identifier indicating the location of the mobile station in the mobile communications network, thereby enabling the identification of the user in the mobile communications network system and the control of the packet transmission.

Abstract translation: 移动通信网络中的地址结构便于分组的路由。 在地址的初始位置处，例如指示表示当前移动通信网络系统的地址结构的类型的前缀等。 在下一个位置，位置地址（LA）位于本发明的特征。 位置地址通常位于子网地址的位置。 为每个移动交换系统提供位置地址（LA），并且在移动交换系统的控制下构成使用移动台的用户的IP地址的一部分。 在最终位置，设置用于识别用户的用户标识符（用户ID），并且为每个用户唯一地提供。 根据本发明的IP地址可以分为上述三个部分，其中的一部分包括指示移动台在移动通信网络中的位置的位置地址和用户标识符，从而能够识别用户在 移动通信网络系统和分组传输的控制。

公开(公告)号：US20060039225A1

公开(公告)日：2006-02-23

申请号：US11203393

申请日：2005-08-12

Applicant: Kazushige Kanda ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Tamio Ikehashi

Inventor： Kazushige Kanda ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Tamio Ikehashi

IPC: G11C5/14

CPC classification number: G11C5/143 ,  G11C17/18

Abstract: A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

公开(公告)号：US07002845B2

公开(公告)日：2006-02-21

申请号：US10957722

申请日：2004-10-05

Applicant: Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

Inventor： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC: G11C16/04

CPC classification number: G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. By use of the semiconductor memory device, occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array can be prevented, and the manufacturing yield can be made high and the operation reliability can be made high without substantially increasing the chip size.

公开(公告)号：US20060034140A1

公开(公告)日：2006-02-16

申请号：US11194608

申请日：2005-08-02

Applicant: Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

Inventor： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC: G11C8/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

Abstract: A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

公开(公告)号：US20060016427A1

公开(公告)日：2006-01-26

申请号：US11168758

申请日：2005-06-29

Applicant: Toshiaki Uda ,  Tsuyoshi Kanda ,  Taisuke Murata ,  Hiroshi Nakamura

Inventor： Toshiaki Uda ,  Tsuyoshi Kanda ,  Taisuke Murata ,  Hiroshi Nakamura

IPC: F02D11/10

CPC classification number: F02D11/106 ,  F02D9/1095 ,  F02D41/20 ,  F02D2041/2058

Abstract: The throttle position corresponding to the rotational angle of the throttle valve is calculated based on electric signals output from a rotor position detector constituted by three Hall ICs that detect the rotational position of a magnet rotor of a brushless DC motor. A valve position control quantity of the throttle valve is so calculated as to eliminate the difference between the thus calculated valve position and a target valve position. The motor current control quantity of the brushless DC motor is so determined as to eliminate the difference between the calculated valve position and the target valve position. Though the throttle position sensor is omitted, the electric signals output from the rotor position detector are used for calculating both the valve position control quantity and the motor current control quantity.

Abstract translation: 基于从检测无刷直流电动机的磁体转子的旋转位置的三个霍尔IC构成的转子位置检测器输出的电信号计算与节流阀的旋转角度对应的节气门位置。 节流阀的阀位控制量被计算为消除由此计算的阀位与目标阀位置之间的差。 无刷直流电动机的电动机电流控制量被确定为消除计算的阀位置和目标阀位置之间的差。 虽然省略了节气门位置传感器，但是从转子位置检测器输出的电信号用于计算阀位控制量和电动机电流控制量。