公开(公告)号：US20130140668A1

公开(公告)日：2013-06-06

申请号：US13312442

申请日：2011-12-06

Applicant: Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

IPC: H01L27/04 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US20130009280A1

公开(公告)日：2013-01-10

申请号：US13177146

申请日：2011-07-06

Applicant: Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

Inventor： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

Abstract translation: 用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。 发射极开口延伸穿过外部基极和电介质层。 电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。 空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

公开(公告)号：US08299547B2

公开(公告)日：2012-10-30

申请号：US12983439

申请日：2011-01-03

Applicant: Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

Inventor： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC: H01L21/336

CPC classification number: H01L29/7824 ,  G06F17/5063 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/785

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract translation: 具有高漏极对体击穿电压（Vb）的横向延伸漏极，金属氧化物半导体场效应晶体管（LEDMOSFET）在漏极漂移区域的相对侧上并入门结构延伸。 延伸部是锥形的，使得每个延伸部和漂移区域之间的距离从邻近通道区域的一端线性地增加到与漏极区域相邻的另一端部。 在一个实施例中，这些扩展可以垂直延伸通过围绕LEDMOSFET的隔离区域。 在另一个实施例中，扩展可以位于隔离区域的顶部。 在任一种情况下，扩展在漏极漂移内产生强大的基本均匀的水平电场分布。 还公开了通过限定扩展的尺寸来形成具有特定Vb的LEDMOSFET的方法以及用于将LEDMOSFET设计为具有特定Vb的程序存储装置。

公开(公告)号：US08299500B2

公开(公告)日：2012-10-30

申请号：US11161936

申请日：2005-08-23

Applicant: Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

Inventor： Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

IPC: H01L29/737

CPC classification number: H01L29/7378 ,  H01L21/8249 ,  H01L29/1004

Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Abstract translation: 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。

公开(公告)号：US20120261719A1

公开(公告)日：2012-10-18

申请号：US13529625

申请日：2012-06-21

Applicant: James S. DUNN ,  Alvin J. JOSEPH ,  Anthony K. STAMPER

Inventor： James S. DUNN ,  Alvin J. JOSEPH ,  Anthony K. STAMPER

IPC: H01L29/78

CPC classification number: H01L29/7378

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract translation: 提供半导体结构和制造半导体的方法涉及异质结双极晶体管。 该结构包括通过金属线在同一布线层上连接的两个器件。 两个器件中的第一个的金属线通过在铜布线结构上选择性地形成金属覆盖层而形成。

公开(公告)号：US20120199907A1

公开(公告)日：2012-08-09

申请号：US13449419

申请日：2012-04-18

Applicant: Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

Inventor： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC: H01L27/12 ,  G06F17/50

CPC classification number: H01L29/93 ,  H01L29/7391

Abstract: A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

Abstract translation: 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

公开(公告)号：US20120190190A1

公开(公告)日：2012-07-26

申请号：US13438508

申请日：2012-04-03

Applicant: James S. DUNN ,  Alvin J. JOSEPH ,  Anthony K. STAMPER

Inventor： James S. DUNN ,  Alvin J. JOSEPH ,  Anthony K. STAMPER

IPC: H01L21/768

CPC classification number: H01L29/7378

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract translation: 提供半导体结构和制造半导体的方法涉及异质结双极晶体管。 该方法包括在相同布线层上形成由金属线连接的两个器件。 两个器件中的第一个的金属线通过在铜布线结构上选择性地形成金属覆盖层而形成。

公开(公告)号：US20120104496A1

公开(公告)日：2012-05-03

申请号：US13345871

申请日：2012-01-09

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L27/1203

Abstract: At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

Abstract translation: 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US20120038024A1

公开(公告)日：2012-02-16

申请号：US12853532

申请日：2010-08-10

Applicant: Alan B. BOTULA ,  Dinh DANG ,  James S. DUNN ,  Alvin J. JOSEPH ,  Peter J. LINDGREN

Inventor： Alan B. BOTULA ,  Dinh DANG ,  James S. DUNN ,  Alvin J. JOSEPH ,  Peter J. LINDGREN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract translation: 绝缘体上硅（SOI）衬底中的低谐波射频（RF）开关及其制造方法。 一种方法包括通过绝缘体层形成至少一个沟槽。 所述至少一个沟槽与形成在所述绝缘体层上的有源区域中的器件相邻。 该方法还包括在绝缘体层之下的衬底中形成至少一个空腔，并从该至少一个沟槽横向延伸到该器件的下方。

公开(公告)号：US20110284961A1

公开(公告)日：2011-11-24

申请号：US13197414

申请日：2011-08-03

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

IPC: H01L29/786 ,  G06F17/50 ,  G06F11/22

CPC classification number: H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

Abstract: A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

Abstract translation: 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。