公开(公告)号：US06525579B1

公开(公告)日：2003-02-25

申请号：US03403670

申请日：1954-01-12

申请人： Ben Joseph Murdock ,  Charles K. Corbett

发明人： Ben Joseph Murdock ,  Charles K. Corbett

IPC分类号： H03K501

CPC分类号： H03K5/125

摘要： In a circuit for producing output pulses which correspond to pre-selected voltage pulses occurring in an input signal train; means connected to derive from said input signal train a succession of unidirectional pulses, at least some of which pulses occur in time coincidence with the leading and trailing edges of said pre-selected voltage pulses; means including a one-shot multi-vibrator connected to receive said unidirectional pulses and produce a first series of pulses having a uniform duration less than the duration of said pre-selected voltage pulses, means including a bi-stable multi-vibrator connected to receive and produce from said first series of pulses a second series of pulses equal to one half the number of pulses in said first series occurring in a given time interval, and means including a discriminator circuit connected to receive said first and second series of pulses and derive a third series of pulses which corresponds to said pre-selected voltage pulses occurring in said input signal train.

摘要翻译： 在用于产生对应于在输入信号列中发生的预选电压脉冲的输出脉冲的电路中; 连接到从所述输入信号序列导出一系列单向脉冲的装置，所述单向脉冲中的至少一些与所述预选电压脉冲的前沿和后沿时间重合; 包括连接以接收所述单向脉冲并且产生具有小于所述预选电压脉冲的持续时间的均匀持续时间的第一序列脉冲的装置，包括连接以接收的双稳态多谐振荡器 并且从所述第一系列脉冲产生等于在给定时间间隔内发生的所述第一序列中的脉冲数量的一半的第二序列脉冲，以及装置，包括连接以接收所述第一和第二串联脉冲并导出 对应于在所述输入信号列中出现的所述预选电压脉冲的第三脉冲序列。

公开(公告)号：US06310409B1

公开(公告)日：2001-10-30

申请号：US09402313

申请日：1999-11-03

申请人： Alain Jolly

发明人： Alain Jolly

IPC分类号： H03K501

CPC分类号： H03K5/01 ,  H03K5/159

摘要： The present invention relates to an optically programmable electric generator of arbitrary time profiles, which comprises a first ultrahigh frequency triggering line (10) and a second ultrahigh frequency discharge line (12) resistively coupled, by points, the first line being triggered by a voltage transition of duration less than one nanosecond, at least one point being taken off from the first line (10) by at least one photoconductor in variable resistance mode, directly coupled to the second line, illuminated by a programmable light source (13). A resistive load is connected at the output (S) of this generator.

摘要翻译： 本发明涉及任意时间轮廓的光学可编程发电机，其包括第一超高频触发线（10）和第二超高频放电线（12），第二超高频放电线（12）通过点电阻耦合，第一线被电压 持续时间小于1纳秒的转变，至少一个点由可变电阻模式的至少一个光电导体从第一线（10）取出，直接耦合到由可编程光源（13）照射的第二线。 电阻负载连接在该发生器的输出端（S）上。

公开(公告)号：US06362671B1

公开(公告)日：2002-03-26

申请号：US09771364

申请日：2001-01-26

申请人： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

发明人： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

IPC分类号： H03K501

摘要： A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

公开(公告)号：US06340913B1

公开(公告)日：2002-01-22

申请号：US09640905

申请日：2000-08-16

申请人： David L. Grundy

发明人： David L. Grundy

IPC分类号： H03K501

CPC分类号： H03H11/04

摘要： A filter circuit comprising a phase advance circuit acting as a high pass filter, a phase retard circuit acting as a low pass filter, and an amplifier connected in series between an input and an output. A positive feedback loop is provided between the input and the output. The electrical characteristics of the phase advance and phase retard circuits are such that interaction between the phase advance and phase retard circuits is substantially prevented. This may be achieved by providing the phase advance and phase retard circuits with simple output buffers or providing internal closed loop negative feedback paths to provide low output impedances. The phase advance and phase retard circuits may comprise multipliers configured to compensate for variations in the values of resistive and capacitive components of the filter circuits.

摘要翻译： 一种滤波电路，包括充当高通滤波器的相位提前电路，充当低通滤波器的相位延迟电路和串联连接在输入和输出之间的放大器。 在输入和输出之间提供正反馈回路。 相位超前和相位延迟电路的电气特性使得基本上防止了相位超前和相位延迟电路之间的相互作用。 这可以通过为相位提前和相位延迟电路提供简单的输出缓冲器或提供内部闭环负反馈路径来实现，以提供低输出阻抗。 相位提前和相位延迟电路可以包括被配置为补偿滤波器电路的电阻和电容分量的值的变化的乘法器。

公开(公告)号：US06307413B1

公开(公告)日：2001-10-23

申请号：US09471914

申请日：1999-12-23

申请人： Kamal Dalmia ,  Anil Agarwal

发明人： Kamal Dalmia ,  Anil Agarwal

IPC分类号： H03K501

CPC分类号： H03L7/087 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/113 ,  H04L7/033

摘要： An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.

摘要翻译： 一种包括第一电路，第二电路和逻辑电路的装置。 第一电路可以被配置为产生具有第一数据速率的第一输出信号，并响应于（i）具有第二数据速率的输入信号和（ii）具有第二数据速率的时钟信号。 响应于（i）输入信号的分割版本和（ii）时钟信号，第二电路可以被配置为产生具有第三数据速率的第二输出信号。 逻辑电路可以被配置为响应于（i）第一输出信号和（ii）第二输出信号而产生时钟信号。

公开(公告)号：US06265920B1

公开(公告)日：2001-07-24

申请号：US09589027

申请日：2000-06-07

申请人： Claude R. Gauthier

发明人： Claude R. Gauthier

IPC分类号： H03K501

CPC分类号： H04L25/028 ,  H04L25/03878

摘要： A method and circuit which allow for pre-emphasis of a high frequency on-chip signal have been developed. The circuit is configured to receive a digital signal from an on-chip source as input for a predriver stage. The method and circuit may use a dual or single predriver stage to equalize the signal when a transition in the value of the digital signal is detected. The single predriver stage circuit equalizes the signal with decreased power and area requirements for greater efficiency.

摘要翻译： 已经开发了允许高频片上信号的预加重的方法和电路。 电路被配置为从片上源接收数字信号作为预驱动级的输入。 当检测到数字信号的转换时，该方法和电路可以使用双或者单个预驱动级来均衡信号。 单个预驱动电路均衡信号，功率和面积要求降低，效率更高。

公开(公告)号：US06249160B1

公开(公告)日：2001-06-19

申请号：US09376496

申请日：1999-08-18

申请人： Hitoyuki Tagami ,  Kuniaki Motoshima

发明人： Hitoyuki Tagami ,  Kuniaki Motoshima

IPC分类号： H03K501

CPC分类号： H03L7/07 ,  H03L7/06 ,  H03L7/0807 ,  H04L7/027 ,  H04L7/0337

摘要： In a clock reproduction and identification device, a clock extraction circuit extracts a transmission line clock from input data and a phase synchronization section reproduces an identification clock synchronized with the transmission line clock in frequency and phase. An identification section identifies the input data based on the identification clock.

摘要翻译： 在时钟再现和识别装置中，时钟提取电路从输入数据中提取传输线时钟，相位同步部分在频率和相位上再现与传输线时钟同步的识别时钟。 识别部分基于识别时钟识别输入数据。

公开(公告)号：US06791386B2

公开(公告)日：2004-09-14

申请号：US10370641

申请日：2003-02-20

申请人： Takanori Saeki

发明人： Takanori Saeki

IPC分类号： H03K501

CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

摘要： A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

摘要翻译： 时钟控制电路包括：控制电路102，用于在参考时钟的每个时钟周期输出作为输入时钟或从输入时钟产生的时钟的参考时钟的相位加或减的控制信号;以及 相位调整电路101馈送输入时钟并输出相位被调整到参考时钟的输出时钟。

公开(公告)号：US06552588B1

公开(公告)日：2003-04-22

申请号：US09972140

申请日：2001-10-05

申请人： Jose M. Cruz-Albrecht

发明人： Jose M. Cruz-Albrecht

IPC分类号： H03K501

CPC分类号： H03K3/84

摘要： One embodiment of the present invention provides a system for generating a pseudo-random non-periodic digital sequence. The system operates by receiving a non-periodic signal at a data input of a flip-flop. This non-periodic signal is sampled at the flip-flop with a clock signal, thereby producing the pseudo-random non-periodic digital sequence at the output of the flip-flop.

摘要翻译： 本发明的一个实施例提供了一种用于产生伪随机非周期数字序列的系统。 该系统通过在触发器的数据输入端接收非周期信号来操作。 这种非周期信号在触发器处用时钟信号进行采样，从而在触发器的输出端产生伪随机非周期数字序列。

公开(公告)号：US06307412B1

公开(公告)日：2001-10-23

申请号：US09323590

申请日：1999-06-01

申请人： Eun-Cheol Kim ,  Kook-Hwan Kwon

发明人： Eun-Cheol Kim ,  Kook-Hwan Kwon

IPC分类号： H03K501

CPC分类号： G11C7/225 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227 ,  H03K5/13 ,  H03K5/15 ,  H03K5/19

摘要： A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

摘要翻译： 时钟监视电路包括分别接收时钟信号和反相时钟信号的第一和第二延迟和时钟信号产生单元。 第一和第二延迟和时钟信号产生单元分别产生第一和第二信号。 逻辑和单元对第一和第二信号进行逻辑加和，以产生停止时钟信号。 根据本发明的时钟监控电路可以监视时钟信号的存在，而与时钟信号的操作周期无关。 此外，利用根据本发明的时钟监视电路的同步半导体存储器件仅在存在时钟信号时才消耗电流。 也就是说，当不存在时钟信号时，该装置不消耗电流，从而在待机模式下减少不必要的电力浪费。