公开(公告)号：US20030085718A1

公开(公告)日：2003-05-08

申请号：US10278287

申请日：2002-10-23

发明人： Lionel Guiraud ,  Patrick Leclerc

IPC分类号： G01R027/04 ,  G01R027/32

CPC分类号： H03K17/603 ,  H03K17/002

摘要： The invention relates to a switching device comprising programmable compensation means which are associated with the input/output connections for inverting the polarity of the input/output connections when said connections present a polarity inversion which is inherent in the conception of the circuits.

摘要翻译： 本发明涉及一种开关装置，其包括与所述输入/输出连接相关联的可编程补偿装置，用于当所述连接呈现电路概念固有的极性反转时，反相输入/输出连接的极性。

公开(公告)号：US06510168B1

公开(公告)日：2003-01-21

申请号：US09669878

申请日：2000-09-27

申请人： Osamu Kikuchi

发明人： Osamu Kikuchi

IPC分类号： H01S300

CPC分类号： H01S5/042 ,  H03K17/603 ,  H03K17/6292 ,  H03K2217/0036

摘要： A drive current Ip used to control the light output from a laser diode LD is controlled by using an output Vsft from a level shift circuit 3. By inserting the level shift circuit 3 between a drive source (V+) and a switch buffer 5, the lower limit (V+)−(V−) of the drive voltage in the circuit is lowered to enable the laser diode drive circuit to be driven at a lower voltage and to achieve a reduction in power consumption.

摘要翻译： 通过使用来自电平移位电路3的输出Vsft来控制用于控制来自激光二极管LD的光输出的驱动电流Ip。通过在驱动源（V +）和开关缓冲器5之间插入电平移位电路3， 降低电路中的驱动电压的下限（V +） - （V-），使得激光二极管驱动电路能够以较低的电压驱动并实现功耗的降低。

公开(公告)号：US20020024370A1

公开(公告)日：2002-02-28

申请号：US09941875

申请日：2001-08-29

发明人： Thomas A. Gaiser ,  Kenneth J. Stern ,  Farhad Vazehgoo ,  Vincenzo DiTommaso ,  William L. Walter ,  Edward B. Hilton

IPC分类号： H03K003/037

CPC分类号： H03K3/012 ,  H03K3/037 ,  H03K17/603 ,  H03K17/6264

摘要： A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

摘要翻译： 精确的SET-RESET逻辑电路和操作方法将锁存功能与产生逻辑输出的关键信号路径分开。 在特定实现中，逻辑电路包括分别由SET和RESET输入控制的两个差分开关对，以及由锁存电路的输出控制的差分对的各个使能电路。 SET和RESET差分开关对响应快于锁存电路以改变输入SET-RESET状态。 最初通过建立通过差分开关和使能电路的第一电流路径响应于新的逻辑输入而产生逻辑输出，然后通过不同的电流路径锁存。

公开(公告)号：US5397932A

公开(公告)日：1995-03-14

申请号：US88153

申请日：1993-07-06

申请人： Claude Barre

发明人： Claude Barre

IPC分类号： H03K17/00 ,  H03K17/60 ,  H03K17/66

CPC分类号： H03K17/603 ,  H03K17/665

摘要： A switching stage includes a differential amplifier configuration. An emitter follower transistor is connected downstream of the differential amplifier configuration. A terminal is provided for a first supply potential. A terminal for a second supply potential is connected to the collector of the emitter follower transistor. A controllable current source is connected between the emitter of the emitter follower transistor and the terminal for the first supply potential. The current source has a control input. A resistor has a first terminal connected to the emitter of the emitter follower transistor and a second terminal connected to a switching stage output. A circuit having a signal output is connected to the first and second terminals of the resistor and to the terminal for the first supply potential, for supplying a signal at the signal output being dependent on the polarity of a voltage dropping at the resistor. The control input of the current source is connected to the signal output of the signal supplying circuit for controlling the current source to cause a high current to flow when the first terminal of the resistor is at a more negative potential than the second terminal of the resistor and to cause a low current to flow when the first terminal of the resistor is at a more positive potential than the second terminal of the resistor.

摘要翻译： 开关级包括差分放大器配置。 射极跟随器晶体管连接在差分放大器配置的下游。 为第一电源提供端子。 用于第二电源电位的端子连接到射极跟随器晶体管的集电极。 可控电流源连接在射极跟随器晶体管的发射极和第一电源电位的端子之间。 当前的源有一个控制输入。 电阻器具有连接到射极跟随器晶体管的发射极的第一端子和连接到开关级输出端的第二端子。 具有信号输出的电路连接到电阻器的第一和第二端子以及用于第一电源电位的端子，用于在信号输出端提供取决于电阻器下降的电压的极性的信号。 电流源的控制输入连接到信号供给电路的信号输出端，用于控制电流源，当电阻器的第一端子处于比电阻器的第二端子更大的负电位时引起高电流流动 并且当电阻器的第一端子处于比电阻器的第二端子更正的电位时，导致低电流流动。

公开(公告)号：US5184028A

公开(公告)日：1993-02-02

申请号：US898998

申请日：1992-06-15

申请人： Don W. Zobel

发明人： Don W. Zobel

IPC分类号： H03K3/0231 ,  H03K17/14 ,  H03K17/60 ,  H03K17/66 ,  H03L7/089

CPC分类号： H03K17/667 ,  H03K17/14 ,  H03K17/603 ,  H03K3/0231 ,  H03L7/0896

摘要： A charge pump circuit (10) has been provided for maintaining the currents sunk by each of the bottom current sources (12, 14) substantially equal to the current sourced from a first upper current source (16). The present invention maintains the voltage across a second upper current source (64) that determines the current for the lower current sources to be modified with respect to corresponding changes in the first upper current source wherein these changes in the first upper current source are due to a varying voltage occurring at the output (18) of the charge pump circuit.

摘要翻译： 已经提供了一种电荷泵电路（10），用于保持每个底部电流源（12,14）下降的电流基本上等于来自第一上部电流源（16）的电流。 本发明保持跨越第二上部电流源（64）的电压，该第二上部电流源确定相对于第一上部电流源中的相应变化要修改的较低电流源的电流，其中第一上部电流源中的这些变化是由于 在电荷泵电路的输出端（18）出现变化的电压。

公开(公告)号：US5151780A

公开(公告)日：1992-09-29

申请号：US491136

申请日：1999-03-09

申请人： David M. Chapman

发明人： David M. Chapman

IPC分类号： H04N5/44 ,  H03F3/45 ,  H03F3/72 ,  H03K17/60

CPC分类号： H03F3/72 ,  H03K17/603

摘要： A differential amplifier includes two transistors T1 and T2 having their collectors connected through respective loads R1 and R2 to one supply line VL1, their emitters connected together and to a controllable constant current source IB which supplies a bias current Ib and which is connected between the common connection of the emitters and a return supply line VL2. The transistor bases are connected to receive a control voltage Vc. The common connection of the emitters is also connected through a by-pass resistance RB to a bias voltage source +VB. The circuit parameters are such that flow of bias current Ib will result in a small current Ir being diverted through the by-pass resistance RB instead of flowing through the transistors. This small current approximates in value to the value of any residual bias current when the curent source IB is switched off, but has a value which is negligible relative to the value of the bias current when the current source IB is switched on.

公开(公告)号：US5140175A

公开(公告)日：1992-08-18

申请号：US651364

申请日：1991-05-03

申请人： Keiji Yagi ,  Kazuhiro Zenba ,  Yukihiro Sekiguchi ,  Fumio Ishikawa ,  Tetsuo Yamamoto ,  Takayuki Aoki

发明人： Keiji Yagi ,  Kazuhiro Zenba ,  Yukihiro Sekiguchi ,  Fumio Ishikawa ,  Tetsuo Yamamoto ,  Takayuki Aoki

IPC分类号： H01S5/042 ,  H03K17/0412 ,  H03K17/60 ,  H05B33/08

CPC分类号： H05B33/0818 ,  H03K17/04126 ,  H03K17/603 ,  H05B33/0803 ,  H01S5/0428 ,  Y02B20/347

摘要： A light-emitting diode drive circuit of the present invention comprises: a current supply circuit (3) including a first transistor (16), the base of which receives a first drive pulse signal (S3) output from a signal input circuit, and a second transistor (15), the collector of which is connected to a light-emitting diode (2), the emitter of which is connected to a current source (24) together with the emitter of the first transistor (16), and the base of which receives a second drive pulse signal (S2) having a phase opposite to that of the first drive pulse signal (S3); a fall time shortening circuit (6) including a third transistor (13) which is connected in parallel with the light-emitting diode (2) and the base of which receives an input for short-circuiting both terminals of the light-emitting diode (2) during a turn-OFF time; and a rise time shortening circuit (5) including a circuit (4) for generating a peaking current during a turn-ON time of the light-emitting diode (2), and a fourth transistor (14) being connected in series with the third transistor (13) and adding the peaking current to the drive current during the turn-ON time of the light-emitting diode (2), wherein rise and fall times of the light pulse output are shortened to greatly increase a response speed of the light-emitting diode (2) having poor inherent response characteristics, such as a red light-emitting diode having a short wavelength range.

公开(公告)号：US5075567A

公开(公告)日：1991-12-24

申请号：US545920

申请日：1990-06-29

申请人： Akihiro Kubota

发明人： Akihiro Kubota

IPC分类号： H03K17/30 ,  H03K17/60 ,  H03K5/08

CPC分类号： H03K17/603 ,  H03K17/30

摘要： An electronic switch circuit generates an output signal which is alternatively brought either into a first condition or into a second condition dependent upon a voltage level of an input signal. The electronic switch circuit includes first and second transistors which are mutually connected to form a differential circuit. A first bias circuit applies a first bias voltage to the first transistor. A second bias circuit applies to the second transistor a second bias voltage of a constant level which is independent of the voltage level of the input signal. The second bias voltage is different from the first bias voltage, when the voltage level of the input signal is smaller than a predetermined voltage level. When the voltage level of the input signal is not smaller than the predetermined voltage level, a control circuit operates to change the bias voltage for the second transistor so as to invert the large-and-small relationship between the bias voltages of the first and second transistors.

摘要翻译： 电子开关电路产生输出信号，该输出信号或者根据输入信号的电压电平进入第一状态或第二状态。 电子开关电路包括相互连接以形成差分电路的第一和第二晶体管。 第一偏置电路将第一偏置电压施加到第一晶体管。 第二偏置电路向第二晶体管施加与输入信号的电压电平无关的恒定电平的第二偏置电压。 当输入信号的电压电平小于预定电压电平时，第二偏压与第一偏置电压不同。 当输入信号的电压电平不小于预定电压电平时，控制电路操作以改变第二晶体管的偏置电压，以便反转第一和第二晶体管的偏置电压之间的大小关系 晶体管。

公开(公告)号：US5059831A

公开(公告)日：1991-10-22

申请号：US494315

申请日：1990-03-16

申请人： Masashi Itoh

发明人： Masashi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H03K17/081 ,  H03K17/16 ,  H03K17/60 ,  H03K17/62

CPC分类号： H03K17/08112 ,  H03K17/16 ,  H03K17/603 ,  H03K17/6242 ,  H03K17/6271

摘要： A buffer circuit comprises an interface node, a bipolar transistor having a collector connected to a first power source, an emitter connected to a second power source, and a base, for transferring a signal supplied to and from the interface node, and a diode structure formed between the emitter and base of the bipolar transistor, the diode structure containing a PN junction reversely coupled across the emitter-base junction of the bipolar transistor.

公开(公告)号：US4835771A

公开(公告)日：1989-05-30

申请号：US256162

申请日：1988-10-07

申请人： Michel Moussie

发明人： Michel Moussie

IPC分类号： H03K3/2885 ,  H03K17/60 ,  H03K17/62

CPC分类号： H03K17/6264 ,  H03K17/603 ,  H03K3/2885

摘要： A multiplexer module includes N input transistors (T.sub.0 to T.sub.3) whose bases receive input signals (E.sub.0 . . . E.sub.3), whose collectors are connected to ground and whose emitters are coupled to those of a multi-emitter output transister T'.sub.4. A logic addressing circuit (ALC) connects a current source I to one of the emitters of the input transistors (T.sub.0 to T.sub.3) as a function of an address (A.sub.0, A.sub.1) received. Any reference voltage on the output transistor (T'.sub.4) is suppressed by short-circuiting its base and its collector which constitutes the output S' which is connected to ground by way of an output resistor R'.sub.s. The module may be connected to other modules (having e.g. K inputs) within the same circuit, notably in order to realize a multiplexer having N.sup.k inputs without giving rise to stray coupling between the outputs of the various modules.

摘要翻译： 多路复用器模块包括N个输入晶体管（T0至T3），其基极接收输入信号（E0。E3），其集电极连接到地，并且其发射极耦合到多发射极输出转换器T'4的发射极。 逻辑寻址电路（ALC）根据所接收的地址（A0，A1）将电流源I连接到输入晶体管的一个发射极（T0至T3）。 输出晶体管（T'4）上的任何参考电压通过使其基极及其集电极短路而被抑制，该集电极构成通过输出电阻器R连接到地的输出S'。 该模块可以连接到同一电路内的其他模块（具有例如K个输入），特别是为了实现具有Nk个输入的多路复用器而不会引起各个模块的输出之间的杂散耦合。