公开(公告)号：US4115711A

公开(公告)日：1978-09-19

申请号：US815266

申请日：1977-07-13

Applicant: Michel Moussie

Inventor： Michel Moussie

IPC: H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H03K3/2893 ,  H03K17/30 ,  H03K19/018 ,  H03K19/08 ,  H03K19/091 ,  H03K5/20

CPC classification number: H01L27/04 ,  H01L27/0233 ,  H01L27/0821 ,  H03K19/01818 ,  H03K19/08 ,  H03K19/091 ,  H03K3/2893

Abstract: A hysteresis threshold circuit including two complementary transistors and an output transistor with an injector controlled by the collector of the second complementary transistor. The emitters of the second transistor and of the output transistor are interconnected, while the input of the circuit is constituted by the emitter of the first complementary transistor.

Abstract translation: 包括两个互补晶体管和具有由第二互补晶体管的集电极控制的注入器的输出晶体管的滞后阈值电路。 第二晶体管和输出晶体管的发射极互连，而电路的输入由第一互补晶体管的发射极构成。

公开(公告)号：US4612460A

公开(公告)日：1986-09-16

申请号：US541946

申请日：1983-10-14

Applicant: Gilbert Y. M. Gloaguen ,  Michel Moussie

Inventor： Gilbert Y. M. Gloaguen ,  Michel Moussie

IPC: H03K19/018 ,  H03K19/092 ,  H03K19/003

CPC classification number: H03K19/01806

Abstract: A circuit for translating signal levels between a logic family type circuit (11) of, for example, the TTL type, and a second logic family type circuit of, for example, the ECL/CML type (12) of, for example, the ECL/CML type, in which a transit terminal (22) receives the output signals of the first logic circuit in order to translate them into input signals for the second logic circuit.The translator circuit comprises a transistor (T1) whose base is connected to a first point (P1) at a chosen potential, which may be common ground (M), via a first forward junction (J1), and is further connected to the transit terminal (22) by a series arrangement (23) of a resistor (R1) and a second junction (J2). The circuit further has a current source (S1) connected between the supply voltage source and the emitter of the transistor T1, and a load element (Z) for the current source (S1) connected to the emitter of the transistor T1 and to a second point (P2) at a chosen potential, which may be the common ground return. One output level of the translator circuit is determined by the voltage drop in the element (Z) traversed by the current of (S1) when the transistor (T1) is cut off, while the other level is determined by the voltage at the emitter of (T1) when it is conducting.

Abstract translation: 用于将例如TTL类型的逻辑家族型电路（11）和诸如例如ECL / CML类型（12）的第二逻辑系列类型电路之间的信号电平转换的电路， ECL / CML类型，其中转接终端（22）接收第一逻辑电路的输出信号，以便将它们转换成用于第二逻辑电路的输入信号。 转换器电路包括晶体管（T1），其晶体管（T1）经由第一正向结（J1）以选定的电位连接到第一点（P1），其可以是公共接地（M），并且还连接到中转 端子（22）由电阻器（R1）和第二结（J2）的串联布置（23）组成。 该电路还具有连接在电源电压源和晶体管T1的发射极之间的电流源（S1）和连接到晶体管T1的发射极的电流源（S1）的负载元件（Z）和第二 点（P2）在选定的电位，这可能是公共地面回报。 转换器电路的一个输出电平由晶体管（T1）截止时由（S1）的电流穿过的元件（Z）中的电压降决定，而另一个电平由发射极的电压 （T1）。

公开(公告)号：US4494135A

公开(公告)日：1985-01-15

申请号：US425147

申请日：1982-09-28

Applicant: Michel Moussie

Inventor： Michel Moussie

IPC: G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L21/822 ,  H01L21/8229 ,  H01L23/525 ,  H01L27/04 ,  H01L27/06 ,  H01L27/102 ,  H01L29/04 ,  H01L27/10 ,  H01L45/00

CPC classification number: H01L27/1021 ,  G11C17/16 ,  H01L23/525 ,  H01L23/5256 ,  H01L27/0688 ,  H01L29/04 ,  H01L2924/0002 ,  Y10S257/926

Abstract: A programmable read-only memory includes a number of programmable memory cells, each of which is formed in a thin layer of semiconductor material which extends on an insulating layer of a semiconductor body. Each programmable memory cell includes a p-n junction diode and an electrically destructible programmation element which are integrally formed in the thin layer of semiconductor material. The programmation element includes a necked-down portion of the thin layer, and this element may also have a p-n junction. The resulting structure yields a memory cell which is simple, highly compact, and which can be easily and reliably manufactured by known methods.

Abstract translation: 可编程只读存储器包括多个可编程存储器单元，每个可编程存储单元形成在半导体材料的薄层上，半导体材料在半导体本体的绝缘层上延伸。 每个可编程存储单元包括一体形成在半导体材料薄层中的p-n结二极管和电可破坏的编程元件。 编程元件包括薄层的颈缩部分，并且该元件也可以具有p-n结。 所得到的结构产生简单，高度紧凑的存储单元，并且可以通过已知方法容易且可靠地制造。

公开(公告)号：US4835771A

公开(公告)日：1989-05-30

申请号：US256162

申请日：1988-10-07

Applicant: Michel Moussie

Inventor： Michel Moussie

IPC: H03K3/2885 ,  H03K17/60 ,  H03K17/62

CPC classification number: H03K17/6264 ,  H03K17/603 ,  H03K3/2885

Abstract: A multiplexer module includes N input transistors (T.sub.0 to T.sub.3) whose bases receive input signals (E.sub.0 . . . E.sub.3), whose collectors are connected to ground and whose emitters are coupled to those of a multi-emitter output transister T'.sub.4. A logic addressing circuit (ALC) connects a current source I to one of the emitters of the input transistors (T.sub.0 to T.sub.3) as a function of an address (A.sub.0, A.sub.1) received. Any reference voltage on the output transistor (T'.sub.4) is suppressed by short-circuiting its base and its collector which constitutes the output S' which is connected to ground by way of an output resistor R'.sub.s. The module may be connected to other modules (having e.g. K inputs) within the same circuit, notably in order to realize a multiplexer having N.sup.k inputs without giving rise to stray coupling between the outputs of the various modules.

Abstract translation: 多路复用器模块包括N个输入晶体管（T0至T3），其基极接收输入信号（E0。E3），其集电极连接到地，并且其发射极耦合到多发射极输出转换器T'4的发射极。 逻辑寻址电路（ALC）根据所接收的地址（A0，A1）将电流源I连接到输入晶体管的一个发射极（T0至T3）。 输出晶体管（T'4）上的任何参考电压通过使其基极及其集电极短路而被抑制，该集电极构成通过输出电阻器R连接到地的输出S'。 该模块可以连接到同一电路内的其他模块（具有例如K个输入），特别是为了实现具有Nk个输入的多路复用器而不会引起各个模块的输出之间的杂散耦合。

公开(公告)号：US4229757A

公开(公告)日：1980-10-21

申请号：US938470

申请日：1978-08-31

Applicant: Michel Moussie

Inventor： Michel Moussie

IPC: G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L21/8229 ,  H01L23/525 ,  H01L27/06 ,  H01L27/102 ,  H01L29/04 ,  H01L27/10

CPC classification number: H01L29/04 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/0688 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/055 ,  Y10S257/926

Abstract: Integrated electrically programmable read only memory cell having at least two back-to-back diodes.A first diode is formed by a planar junction (7) between two superimposed regions (2, 6), the second diode is programmable and is formed by a lateral junction (11) between two coplanar zones (9, 10) of a thin semi-conductor layer isolated from the body by an insulating layer (8) having a contact aperture (18).

Abstract translation: 具有至少两个背对背二极管的集成电可编程只读存储单元。 第一二极管由两个叠加区域（2,6）之间的平面结（7）形成，第二二极管是可编程的，并且由半薄型半平面的两个共面区域（9,10）之间的横向结（11）形成。 - 导体层通过具有接触孔（18）的绝缘层（8）与本体隔离。

公开(公告)号：US3976983A

公开(公告)日：1976-08-24

申请号：US549065

申请日：1975-02-11

Applicant: Michel Moussie

Inventor： Michel Moussie

IPC: G11C17/00 ,  G11C17/08 ,  G11C17/16

CPC classification number: G11C17/16

Abstract: A read-only memory which can be programmed by means of internal fuses and whose memory cells are formed by bipolar transistors in an ECL circuit.The emitters of the memory-position transistors are coupled to the emitter in a row-address transistor, the bases are connected directly to the emitter of a column read transistor, the collector lines include the fuses, and the rows and columns are supplied from current sources.

Abstract translation: 可以通过内部熔丝编程的只读存储器，其存储单元由ECL电路中的双极晶体管形成。