公开(公告)号：US09680474B1

公开(公告)日：2017-06-13

申请号：US15073389

申请日：2016-03-17

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Srinivasa L. Karumajji ,  Santosh Yachareni ,  Sandeep Vundavalli ,  Udaya Kumar Bobbili ,  Golla V S R K Prasad

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17784

Abstract: An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。

公开(公告)号：US10466275B1

公开(公告)日：2019-11-05

申请号：US16022403

申请日：2018-06-28

Applicant: Xilinx, Inc.

Inventor： Sandeep Vundavalli ,  Sree RKC Saraswatula ,  James D. Wesselkamper ,  Santosh Yachareni ,  Shidong Zhou ,  Anil Kumar Kandala

IPC: G11C29/00 ,  G01R11/24 ,  G01R31/30 ,  G06F21/86 ,  G06F21/76 ,  G01R22/06

Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

公开(公告)号：US10069487B1

公开(公告)日：2018-09-04

申请号：US15463824

申请日：2017-03-20

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Santosh Yachareni ,  Sandeep Vundavalli ,  Vijay Kumar Koganti ,  Golla V S R K Prasad ,  Udaya Kumar Bobbili

IPC: H03H11/26 ,  H03K3/3565 ,  H03K19/173 ,  H03K19/177

Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.