-
公开(公告)号：US10551705B2
公开(公告)日：2020-02-04
申请号：US16110197
申请日：2018-08-23
Inventor： Xiaohui Nie , Zhihao Cao , Qi Ding
IPC: G06F3/041 , G02F1/1362 , H01L27/12 , H01L29/786 , G02F1/1333 , G02F1/1368 , G06F3/044 , G02F1/136
Abstract: The present invention relates to a display panel technology field. An array substrate comprises a first metal layer, a buffer layer, a semiconductor layer, an insulating layer, a scanning metal layer, an inter layer dielectric, and a second metal layer that are sequentially stacked on a glass substrate along a first direction, and a first pixel set and a second pixel set that are arranged alternately along a second direction; and a first conductive path sequentially connecting the first pixel set and a second conductive path sequentially connecting the second pixel set. The first conductive path and the second conductive path change lines alternately in the first metal layer and the second metal layer, such that the first pixel set and the second pixel set are sequentially connected in series. With the array substrate of the present invention, the metal layer for changing line can be eliminated.
-
Patent Agency Ranking
公开(公告)号：US11205666B2
公开(公告)日：2021-12-21
申请号：US16306589
申请日：2018-08-07
Inventor： Zhihao Cao
Abstract: An array substrate and a display panel are provided. The array substrate includes a first region and a second region. The first region corresponds to a display region of the display panel. The second region corresponds a non-display region of the display panel. The second region includes a substrate and an electrically conductive line formed on the substrate. The second region further includes at least one metal pattern formed between the substrate and the electrically conductive line.
-
3.发明授权公开(公告)号：US10725570B2
公开(公告)日：2020-07-28
申请号：US15735785
申请日：2017-10-19
Inventor： Shuanghua Zeng , Zhihao Cao
IPC: G02F1/1362 , G06F3/041 , H01L21/56 , H01L21/768 , H01L23/50
Abstract: An integrated circuit pin is provided. The integrated circuit pin includes a glass substrate, a buffer layer above the glass substrate, a gate insulating layer above the buffer layer, a first metal layer above the gate insulating layer, a second metal layer above the first metal layer, a first insulating layer above the second metal layer, a second insulating layer above the first insulating layer, a bottom indium tin oxide (BITO) above the second insulating layer, and a top indium tin oxide covering the BITO. The BITO further extends downwardly along the inner wall of a through-hole penetrating through the first and second insulating layers such that the BITO is connected to the second metal layer. An in-cell touch panel is also provided. According to the disclosure, the thickness of the conductive layer can be increased. The anti-external interference and the drop reliability of ITP products can be enhanced.
-
公开(公告)号：US10566354B2
公开(公告)日：2020-02-18
申请号：US16040636
申请日：2018-07-20
Inventor： Zhihao Cao , Xiaohui Nie , Zhandong Zhang
Abstract: An array substrate used for a touch display screen is provided. The array substrate comprises a substrate; a polysilicon layer disposed on the substrate; a dielectric layer disposed on the polysilicon layer and the substrate; a touch line, a connecting line and data line arranged sequentially at intervals on the dielectric layer; a planarization layer covering the connecting line and data line; wherein a first through-hole and second through-hole arranged sequentially at intervals are formed on planarization layer, the touch line is facing and exposed from first through-hole; a portion of the connecting line is facing and exposed from second through-hole; a source and drain in contact with a portion of the surface of polysilicon layer are formed in dielectric layer arranged at intervals, the drain and source are respectively connected with the connecting line and data line, and the first through-hole is completely misplaced with the second through-hole.
-
公开(公告)号：US11996415B2
公开(公告)日：2024-05-28
申请号：US16966015
申请日：2020-07-21
Inventor： Zhihao Cao , Wei Tang , Jianlong Huang
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , H01L27/1259 , G02F1/136222 , G02F1/136295 , G02F1/1368
Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes a substrate and a transistor layer. The transistor array layer includes a first metal layer disposed above the substrate. The first metal layer includes a gate, a second metal layer disposed above the first metal layer. The second metal layer includes a source, a drain, and a metal trace, and at least one repair part disposed on both sides of the metal trace. The repair part and the metal trace are configured to form a signal trace.
-
公开(公告)号：US11881147B2
公开(公告)日：2024-01-23
申请号：US17048775
申请日：2020-09-10
Inventor： Zhihao Cao , Wei Tang , Yongbo Wu
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2300/02 , G09G2300/0408 , G09G2300/0426
Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a plurality of scan lines parallel to one another, a plurality of data lines parallel to one another, a common electrode, and a plurality of connection lines. The scan lines and the data lines are disposed in different layers and perpendicular to each other. A loop of a second metal layer is disposed in a non-display region in the layer in which the data lines are disposed. A plurality of connection lines are disposed to be parallel to the data lines. A plurality of protrusion structures are disposed on the scan lines at intervals along a first direction.
-
-
-
-
-
Search Results
6
records
(took 0.047 seconds)
