公开(公告)号：US12276886B2

公开(公告)日：2025-04-15

申请号：US18470450

申请日：2023-09-20

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Jing Lv ,  Teng Wu ,  Li Zhang

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/1362

Abstract: A curved display panel includes a first substrate, pixel units disposed on the first substrate, and black matrices disposed on a side of the sub-pixel away from the first substrate. Each of the pixel units includes a plurality of sub-pixels disposed in an array along a first direction and a second direction, each of the sub-pixels includes a long side and a short side, the long side extends along the first direction, the short side extends along the second direction. Each of the black matrices includes a first sub-part and a second sub-part, an orthographic projection of the first sub-part on the first substrate is located at an interval between orthographic projections of two adjacent sub-pixels on the first substrate, and an orthographic projection of the second sub-part on the first substrate overlaps with an orthographic projection of the short side of the sub-pixel on the first substrate.

公开(公告)号：US20220358891A1

公开(公告)日：2022-11-10

申请号：US17280909

申请日：2020-11-26

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jing Lv

IPC: G09G3/36

Abstract: The invention provides a GOA circuit and driving method therefor, and a display panel. The GOA circuit includes a GOA unit. The GOA unit includes a forward and reverse scan control module, a node signal control module, a voltage regulator module, an output control module, a first pull-down module, and a second pull-down module. When the second pull-down module is in operation, the forward and reverse scan control module controls the voltage regulator module to be in an off state, so that the GOA circuit has no transistor in the on state for a long time, thus to suppress threshold voltage drift in transistors.

公开(公告)号：US12205555B2

公开(公告)日：2025-01-21

申请号：US17622758

申请日：2021-12-15

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jing Lv ,  Guoyu Zhang ,  Yuhang Jiang

IPC: G09G3/36

Abstract: A gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units, wherein a Nth stage gate driving unit includes a pull-up control module and a node signal control module. By an adjustment of the signals connected to a first input terminal, a second input terminal, a first control terminal, and a second control terminal of the node signal control module, an original driving time sequence can be realized without using a clock signal, which reduces a space occupied by a frame.

公开(公告)号：US11798511B2

公开(公告)日：2023-10-24

申请号：US17280909

申请日：2020-11-26

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jing Lv

IPC: G09G3/36 ,  G06F3/041

CPC classification number: G09G3/3677 ,  G06F3/04166 ,  G09G3/3696 ,  G06F3/0412 ,  G09G2300/0842 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061

Abstract: The invention provides a GOA circuit and driving method therefor, and a display panel. The GOA circuit includes a GOA unit. The GOA unit includes a forward and reverse scan control module, a node signal control module, a voltage regulator module, an output control module, a first pull-down module, and a second pull-down module. When the second pull-down module is in operation, the forward and reverse scan control module controls the voltage regulator module to be in an off state, so that the GOA circuit has no transistor in the on state for a long time, thus to suppress threshold voltage drift in transistors.

公开(公告)号：US20240038193A1

公开(公告)日：2024-02-01

申请号：US17622758

申请日：2021-12-15

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jing Lv ,  Guoyu Zhang ,  Yuhang Jiang

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/08

Abstract: A gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units, wherein a Nth stage gate driving unit includes a pull-up control module and a node signal control module. By an adjustment of the signals connected to a first input terminal, a second input terminal, a first control terminal, and a second control terminal of the node signal control module, an original driving time sequence can be realized without using a clock signal, which reduces a space occupied by a frame.