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Patent Agency Ranking
1.发明申请公开(公告)号：US20190386027A1
公开(公告)日：2019-12-19
申请号：US15579250
申请日：2017-10-18
Inventor： Jiawei ZHANG
IPC: H01L27/12 , H01L29/66 , H01L29/786 , H01L29/423 , H01L29/49
Abstract: A display panel, a display device and a method for preparing a low-temperature polysilicon thin film transistor are provided. The method includes: providing a base substrate; forming a semiconducting layer on the base substrate; forming a first insulating layer on the semiconducting layer; forming a first metal layer on the first insulating layer and pattering the first metal layer to obtain a first metal gate layer; forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer and patterning the second metal layer to obtain a second metal gate layer; forming a third insulating layer on the second metal layer; forming a third metal layer on the third insulating layer and patterning the third metal layer to form a source and a drain. The LTPS technology can be applied to the production of large-size panels by adopting the present disclosure.
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公开(公告)号：US20210080790A1
公开(公告)日：2021-03-18
申请号：US16071525
申请日：2018-05-22
Inventor： Yuebai HAN , Jiawei ZHANG
IPC: G02F1/1362 , G02F1/1333 , H01L27/12 , G02F1/1368
Abstract: Provided are a display device and an array substrate thereof. The array substrate includes a plurality of pixel units arranged in an array, wherein each of the pixel units comprises a light shielding layer, a thin film transistor, a touch electrode, a scan line and a data line, and the scan line is disposed in a first direction, and the data line is disposed in a second direction, and the scan line crosses the data line, and the pixel unit further comprises a touch signal line, and the touch signal line is at a same layer as the scan line, and two adjacent touch signal lines in the first direction are connected with the light shielding layer, the touch signal line is connected to the light shielding layer through a first via hole, and the touch signal line is connected to the touch electrode through a second via hole.
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公开(公告)号：US20200272006A1
公开(公告)日：2020-08-27
申请号：US16343782
申请日：2018-11-19
Inventor： Xiaohui NIE , Jiawei ZHANG
IPC: G02F1/1362 , G02F1/1345 , G02F1/1368
Abstract: A display panel circuit structure is provided. The display panel circuit structure includes: a display area and an output bonding area located on a side of the display area. The output bonding area includes: a plurality of first bonding pads arranged in parallel at intervals, and a plurality of first connecting lines between corresponding first bonding pads of the first bonding pads. Each of the first bonding pads includes: a first bottom pad, a first middle pad, and a first top pad. The first bottom pad and the first connecting lines are all located at a first metal layer, the first middle pad is located at a second metal layer, the first top pad is located at a transparent, electrically conductive layer, the first metal layer, the second metal layer, and the transparent, electrically conductive layer are stacked in order, an insulating interlayer is disposed between the first metal layer and the second metal layer, and a passivation layer is disposed between the second metal layer and the transparent, electrically conductive layer. By disposing the first connecting lines at the first metal layer, when a chip is pressed, a problem that any of the first connecting lines between the corresponding first bonding pins of the first bonding pins is short-circuited with any of the corresponding first bonding pins of the first bonding pins is prevented. Therefore, a process yield is improved, and product quality is ensured.
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4.发明申请公开(公告)号：US20200227538A1
公开(公告)日：2020-07-16
申请号：US16467046
申请日：2019-03-22
Inventor： Xiaohui NIE , Jiawei ZHANG
IPC: H01L29/66 , H01L29/786 , H01L21/265
Abstract: The present application provides a thin film transistor, a method of manufacturing a thin film transistor, and a manufacturing system. The thin film transistor includes a substrate, a buffer layer, an active layer, and a gate insulating layer. A side area of the active layer is doped and modified, so that a surface of the side area is formed as a high resistance area, and then the gate insulating layer is formed by a chemical deposition process, thereby to avoid a weak channel current produced by unintentional electrically conduction of a boundary of the active layer due to a thinner thickness of the gate insulating layer when operating, thereby increasing electrical reliability of the thin film transistor.
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公开(公告)号：US20170243896A1
公开(公告)日：2017-08-24
申请号：US15143627
申请日：2016-05-01
Inventor： Jiawei ZHANG
IPC: H01L27/12 , G02F1/1333 , G02F1/1362 , H01L29/786 , G02F1/1343
CPC classification number: H01L27/1222 , G02F1/133345 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F2001/133357 , G02F2001/134372 , H01L27/124 , H01L29/78609 , H01L29/78618 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L29/78675
Abstract: Provided are an array substrate and a liquid crystal display device. The array substrate includes a base plate and a low temperature poly-silicon layer, a first insulation layer, a gate zone, a second insulation layer, a source zone, a drain zone, a planarization layer, a first transparent conductive layer, a third insulation layer, and a second transparent conductive layer that are arranged on the same side of the base plate. The gate zone covers the first insulation layer. The source zone and the drain zone are respectively connected to two ends of the low temperature poly-silicon layer. The second transparent conductive layer is connected to the drain zone and the second transparent conductive layer includes a plurality of spaced conductive zones.
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