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公开(公告)号：US11276653B2
公开(公告)日：2022-03-15
申请号：US16656233
申请日：2019-10-17
Inventor： Shih-Yuan Chen , Jiun-Yun Li , Rui-Fu Xu , Chiung-Yu Chen , Ting-I Yeh , Yu-Jui Wu , Yao-Chun Chang
Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
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Patent Agency Ranking
公开(公告)号：US11088108B2
公开(公告)日：2021-08-10
申请号：US16454350
申请日：2019-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Yao Yang , Ling-Wei Li , Yu-Jui Wu , Cheng-Lin Huang , Chien-Chen Li , Lieh-Chuan Chen , Che-Jung Chu , Kuo-Chio Liu
IPC: H01L21/48 , H01L23/00 , H01L21/768
Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
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公开(公告)号：US20170203962A1
公开(公告)日：2017-07-20
申请号：US15182754
申请日：2016-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Hsi-Cheng Hsu , Hsin-Yu Chen , Ji-Hong Chiang , Jui-Chun Weng , Wei-Ding Wu , Yu-Jui Wu , Ching-Hsiang Hu , Ming-Tsung Chen
CPC classification number: B81C1/00285 , B81B7/0038 , B81B2201/0235 , B81B2201/0242 , B81B2207/012 , B81B2207/07 , B81C2203/0118 , B81C2203/0792
Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.
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公开(公告)号：US09884758B2
公开(公告)日：2018-02-06
申请号：US15182754
申请日：2016-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Hsi-Cheng Hsu , Hsin-Yu Chen , Ji-Hong Chiang , Jui-Chun Weng , Wei-Ding Wu , Yu-Jui Wu , Ching-Hsiang Hu , Ming-Tsung Chen
CPC classification number: B81C1/00285 , B81B7/0038 , B81B2201/0235 , B81B2201/0242 , B81B2207/012 , B81B2207/07 , B81C2203/0118 , B81C2203/0792
Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.
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公开(公告)号：US09966427B2
公开(公告)日：2018-05-08
申请号：US15154027
申请日：2016-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Hung-Lin Chen , Jui-Chun Weng , Shiuan-Jeng Lin , Tian Sheng Lin , Yu-Jui Wu , Albion Pan , Bob Sun
IPC: H01L49/02 , H01L23/522 , H01L21/3213 , H01L21/311
CPC classification number: H01L28/75 , H01L21/31111 , H01L21/32139 , H01L23/5223
Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.
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公开(公告)号：US20170330931A1
公开(公告)日：2017-11-16
申请号：US15154027
申请日：2016-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shyh-Wei Cheng , Hung-Lin Chen , Jui-Chun Weng , Shiuan-Jeng Lin , Tian Sheng Lin , Yu-Jui Wu , Albion Pan , Bob Sun
IPC: H01L49/02 , H01L21/311 , H01L21/3213 , H01L23/522
CPC classification number: H01L28/75 , H01L21/31111 , H01L21/32139 , H01L23/5223
Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.
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