公开(公告)号：US11145709B2

公开(公告)日：2021-10-12

申请号：US16439636

申请日：2019-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hong-Yang Chen ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC: H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L49/02 ,  H01L27/01 ,  H01L27/06

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

公开(公告)号：US09966427B2

公开(公告)日：2018-05-08

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

公开(公告)号：US20170330931A1

公开(公告)日：2017-11-16

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.