公开(公告)号：US11557508B2

公开(公告)日：2023-01-17

申请号：US16994091

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Wei-Li Huang ,  Sheng-Pin Yang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04 ,  H01F17/00 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.

公开(公告)号：US20220230978A1

公开(公告)日：2022-07-21

申请号：US17326941

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48 ,  H01L49/02

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

公开(公告)号：US20230369269A1

公开(公告)日：2023-11-16

申请号：US18360425

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L28/60 ,  H01L21/4853 ,  H01L23/5226

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

公开(公告)号：US10748810B2

公开(公告)日：2020-08-18

申请号：US15991523

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Wei-li Huang ,  Sheng-Pin Yang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/04 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04 ,  H01F17/00 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.

公开(公告)号：US11855028B2

公开(公告)日：2023-12-26

申请号：US17326941

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/10 ,  H01L24/17 ,  H01L28/60

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.