公开(公告)号：US3570195A

公开(公告)日：1971-03-16

申请号：US3570195D

申请日：1968-11-13

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： OTSUKA MICHIO ,  SUGIOKA SYUJI

IPC: H01L21/304 ,  H01L29/00 ,  B24C1/00

CPC classification number: H01L21/3046 ,  H01L29/00

Abstract: A METHOD OF FORMING IN A SEMICONDUCTOR SUBSTRATE A RECESS WHOSE DEPTH CAN BE CONTROLLED EXACTLY TO A DESIRED EXTENT, WHICH COMPRISES THE STEPS OF GENERATING A DEPLETION LAYER NEAR AND AT THE PN JUNCTION OF SAID SUBSTRATE, BORING A PART OF SAID SUBSTRATE STARTING WITH THE EXPOSED SURFACE DOWN TO THE DEPLETION LAYER THEREOF SO AS TO CAUSE THE CURRENT FLOWING THROUGH THE PN JUNCTION TO ATTAIN A CERTAIN LEVEL.

公开(公告)号：US3619738A

公开(公告)日：1971-11-09

申请号：US3619738D

申请日：1970-10-12

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： OTSUKA MICHIO

IPC: H01L23/482 ,  H01L29/00 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/744 ,  H01L5/02

CPC classification number: H01L29/744 ,  H01L23/4824 ,  H01L29/00 ,  H01L29/0813 ,  H01L29/102 ,  H01L29/41708 ,  H01L29/41716 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor device with a control grid and comprising at least three semiconductor layers of alternately different conductivity types, portions of the second layer are protruded through the first layer to be exposed on the surface of the first layer, second electrode is mounted on the exposed portions in ohmic contact therewith, a third electrode is mounted to insulating cover the second electrode and the exposed portions containing the same, and the third electrode is in ohmic contact with the first layer.

公开(公告)号：US3559006A

公开(公告)日：1971-01-26

申请号：US3559006D

申请日：1968-11-14

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： OTSUKA MICHIO ,  MURAMATSU HISAYOSHI

IPC: H01L21/00 ,  H01L23/31 ,  H01L29/00 ,  H01L29/06 ,  H01L11/10

CPC classification number: H01L29/0661 ,  H01L21/00 ,  H01L23/3178 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

Abstract: A SEMICONDUCTOR DEVICE HAVING A HIGH RESISTIVITY LAYER AND A LOW RESISTIVITY LAYER FORMED ON ONE SIDE OF SAID HIGH RESISTIVITY LAYER, WITH A PN JUNCTION DEFINED THEREBETWEEN, WHEREIN THERE IS FORMED A SURROUNDING GROOVE EXTENDING FROM THE LOW RESISTIVITY LAYER TO THE HIGH

RESISTIVITY LAYER IN A MANNER TO INCLINE INWARDLY TOWARD THE CENTRAL AXIS OF THE SEMICONDUCTOR APPARATUS, WITH THE BOTTOM OF SAID GROOVE DISPOSED IN THE HIGH RESISTIVITY LAYER.