公开(公告)号：US20200320028A1

公开(公告)日：2020-10-08

申请号：US16909396

申请日：2020-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Edwin HUBBARD ,  Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN ,  Mark Edward WENTROBLE

IPC: G06F13/24 ,  G06F13/42

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

公开(公告)号：US20190354125A1

公开(公告)日：2019-11-21

申请号：US16235631

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Edwin HUBBARD ,  Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN

IPC: G05F1/46 ,  H03K3/3565 ,  H03K5/24 ,  H03K17/00

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

公开(公告)号：US20220014160A1

公开(公告)日：2022-01-13

申请号：US17487241

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN ,  Richard Edwin HUBBARD

IPC: H03F3/45 ,  H04L12/40

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

公开(公告)号：US20200350879A1

公开(公告)日：2020-11-05

申请号：US16862089

申请日：2020-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN ,  Richard Edwin HUBBARD

IPC: H03F3/45 ,  H04L12/40

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

公开(公告)号：US20210167989A1

公开(公告)日：2021-06-03

申请号：US17063450

申请日：2020-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN ,  Wesley Ryan RAY ,  Dushmantha Bandara RAJAPAKSHA

IPC: H04L12/40 ,  H04M3/02

Abstract: A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

公开(公告)号：US20200326738A1

公开(公告)日：2020-10-15

申请号：US16914938

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Richard Edwin HUBBARD ,  Richard Sterling BROUGHTON ,  Vijayalakshmi DEVARAJAN

IPC: G05F1/46 ,  H03K17/00 ,  H03K5/24 ,  H03K3/3565

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

公开(公告)号：US20200264643A1

公开(公告)日：2020-08-20

申请号：US16459107

申请日：2019-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deep BANERJEE ,  Lokesh Kumar GUPTA ,  Abhijeeth AAREY PREMANATH ,  Richard Sterling BROUGHTON

IPC: G05F1/56 ,  H04L12/40 ,  H04B1/40

Abstract: A bus transceiver circuit including a current source device, a current mirror coupled to the current source device, and a first transistor having a first control input and first and second current terminals. The bus transceiver circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the first control input at a first node. The fourth current terminal is coupled to the current mirror. A resistor is coupled between the first current terminal and the first node.