公开(公告)号：US20200228303A1

公开(公告)日：2020-07-16

申请号：US16831867

申请日：2020-03-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Michael Gerald VRAZEL

IPC: H04L7/033 ,  H03L7/087 ,  H03L7/093 ,  H03L7/091 ,  H03L7/095

Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.

公开(公告)号：US20220085967A1

公开(公告)日：2022-03-17

申请号：US17019673

申请日：2020-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Gerald VRAZEL

IPC: H04L7/00

Abstract: Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

公开(公告)号：US20230208608A1

公开(公告)日：2023-06-29

申请号：US18111873

申请日：2023-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Gerald VRAZEL

IPC: H04L7/00

CPC classification number: H04L7/0016

Abstract: Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.