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公开(公告)号：US20240274173A1
公开(公告)日：2024-08-15
申请号：US18498267
申请日：2023-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Cheolhui LEE , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC classification number: G11C7/222 , G11C7/1081 , G11C7/14 , G11C7/225
Abstract: Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.
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公开(公告)号：US20210359684A1
公开(公告)日：2021-11-18
申请号：US17389148
申请日：2021-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号：US20210335427A1
公开(公告)日：2021-10-28
申请号：US17121015
申请日：2020-12-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyo KIM , Daeseok Byeon , Youngmin JO , Seungwon Lee
IPC: G11C16/22 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.
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4.发明公开公开(公告)号：US20240257848A1
公开(公告)日：2024-08-01
申请号：US18494258
申请日：2023-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwanseok KU , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC classification number: G11C7/222 , G11C7/1057 , G11C8/18
Abstract: A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.
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Patent Agency Ranking
公开(公告)号：US20240096382A1
公开(公告)日：2024-03-21
申请号：US18464618
申请日：2023-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Junghwan KWAK , Seungjun BAE , Chiweon YOON , Byungkwan CHUN , Youngmin JO
CPC classification number: G11C7/1048 , G06F13/16 , G06F2213/16 , G11C2207/2254
Abstract: A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.
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公开(公告)号：US20210375347A1
公开(公告)日：2021-12-02
申请号：US17196183
申请日：2021-03-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Taehyo Kim , Daeseok Byeon , Seungwon Lee
IPC: G11C11/4072 , G11C11/4099 , G11C11/4093 , G11C5/06
Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.
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公开(公告)号：US20250123776A1
公开(公告)日：2025-04-17
申请号：US18999741
申请日：2024-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US20220229599A1
公开(公告)日：2022-07-21
申请号：US17528285
申请日：2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US20210242870A1
公开(公告)日：2021-08-05
申请号：US17021728
申请日：2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , H03K19/08 , G11C7/10 , G11C8/10
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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