公开(公告)号：US20220157822A1

公开(公告)日：2022-05-19

申请号：US17392775

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung AHN ,  Yongseok AHN ,  Hyunyong KIM ,  Minsub UM ,  Ju Hyung WE ,  Joonkyu RHEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

公开(公告)号：US20220149048A1

公开(公告)日：2022-05-12

申请号：US17357139

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonkyu RHEE ,  Jiyoung AHN ,  Hyunyong KIM ,  Jamin KOO ,  Yongseok AHN ,  Minsub UM ,  Sangho LEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

公开(公告)号：US20220271043A1

公开(公告)日：2022-08-25

申请号：US17744026

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

公开(公告)号：US20210104529A1

公开(公告)日：2021-04-08

申请号：US16902506

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.