公开(公告)号：US20140080302A1

公开(公告)日：2014-03-20

申请号：US13966345

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tsukasa MATSUDA ,  Jinnam KIM ,  Jongho YUN ,  Jongmyeong LEE

IPC: H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成第一牺牲层，所述第一牺牲层包括导电材料，在所述第一牺牲层上形成第二牺牲层，所述第二牺牲层包括绝缘材料，图案化所述第二牺牲层 层和第一牺牲层，以形成连续穿过第二和第一牺牲层的开口，在包括开口的第二和第一牺牲层上保形地形成晶种层，并且通过电镀形成填充具有晶种层的开口的导电图案 处理。

公开(公告)号：US20190189540A1

公开(公告)日：2019-06-20

申请号：US16282682

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Tsukasa MATSUDA ,  Rak-Hwan KIM ,  Byung-Hee KIM ,  Nae-In LEE ,  Jong-Jin LEE

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

公开(公告)号：US20150115398A1

公开(公告)日：2015-04-30

申请号：US14453310

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok LEE ,  Jongmin BAEK ,  Dohyoung KIM ,  Tsukasa MATSUDA ,  Youngwoo CHO ,  Jongseo HONG

IPC: H01L21/768 ,  H01L21/764 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02296 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Abstract translation: 制造半导体器件的方法可以包括：在衬底上形成具有开口的层间绝缘层; 在开口和层间绝缘层上形成金属层，金属层包括在每个开口的侧壁上的侧壁部分和在每个开口的底表面上的底部，其中底部部分比 侧壁部分; 回流金属层以在开口中形成金属图案，金属图案具有位于层间绝缘层的最上表面以下的顶表面; 和/或形成覆盖开口中的金属图案的覆盖图案。