公开(公告)号：US20130275838A1

公开(公告)日：2013-10-17

申请号：US13787342

申请日：2013-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Thomas Michael Henige

IPC: H03M13/13

CPC classification number: H03M13/1145 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/114 ,  H03M13/13

Abstract: A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many code blocks as stages. A controller passes the code blocks between the processing stages at the proper time and in the proper sequence. The controller passes the code blocks through the series of stages in a time-division multiplexed fashion.

Abstract translation: 低密度奇偶校验解码器包括分为串联布置的两个或多个处理级的解码处理。 一次，每个处理阶段处理与系列中的每个处理阶段不同的代码块。 解码器能够同时解码多个代码块作为阶段。 控制器在正确的时间和正确的顺序在处理阶段之间传递代码块。 控制器以时分复用的方式将代码块传送通过一系列级。

公开(公告)号：US20150207523A1

公开(公告)日：2015-07-23

申请号：US14599325

申请日：2015-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shadi Abu-Surra ,  Eran Pisek ,  Thomas Michael Henige ,  Sridhar Rajagopal

IPC: H03M13/11

CPC classification number: H03M13/1131 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1168 ,  H03M13/6591 ,  H03M13/6594

Abstract: A low density parity check decoder is provided that includes a variable-node (VN) processing domain comprising high-bit resolution processing circuitry, a check-node (CN) processing domain comprising low-bit resolution processing circuitry lower than the high-bit resolution processing circuitry, and mapping circuitry configured to transfer a message between the VN processing domain and the CN processing domain.

Abstract translation: 提供了一种低密度奇偶校验解码器，其包括包括高位分辨率处理电路的可变节点（VN）处理域，包括低于高位分辨率的低位分辨率处理电路的校验节点（CN）处理域 处理电路和配置成在VN处理域和CN处理域之间传送消息的映射电路。

公开(公告)号：US09015568B2

公开(公告)日：2015-04-21

申请号：US13787342

申请日：2013-03-06

Applicant: Samsung Electronics Co., Ltd

Inventor： Thomas Michael Henige

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/13

CPC classification number: H03M13/1145 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/114 ,  H03M13/13

Abstract: A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many code blocks as stages. A controller passes the code blocks between the processing stages at the proper time and in the proper sequence. The controller passes the code blocks through the series of stages in a time-division multiplexed fashion.

Abstract translation: 低密度奇偶校验解码器包括分为串联布置的两个或多个处理级的解码处理。 一次，每个处理阶段处理与系列中的每个处理阶段不同的代码块。 解码器能够同时解码多个代码块作为阶段。 控制器在正确的时间和正确的顺序在处理阶段之间传递代码块。 控制器以时分复用的方式将代码块传送通过一系列级。