公开(公告)号：US20220172944A1

公开(公告)日：2022-06-02

申请号：US17385069

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Seung HA ,  Jang Hoon KIM ,  Tae-Kyu KIM ,  Young Kuk BYUN ,  Jong Hyun JUNG

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor device includes forming a first lower overlay key including first and second patterns in a lower layer, forming a first upper overlay key including third and fourth patterns in an upper layer vertically disposed on the lower layer, irradiating a first measurement light to a first region of interest (ROI) over first portions of the first and second patterns to detect a first overlay error and irradiating a second measurement light to a second ROI over second portions of the first and second patterns, the second ROI being different from the first ROI, to detect a second overlay error.

公开(公告)号：US20210050221A1

公开(公告)日：2021-02-18

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin KIM ,  Byung-Hyun LEE ,  Yoonyoung CHOI ,  Tae-Kyu KIM ,  Heesook CHEON ,  Bo-Wo CHOI ,  Hyun-Sil HONG

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.