公开(公告)号：US11309014B2

公开(公告)日：2022-04-19

申请号：US17143619

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Sungoh Ahn

IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/18 ,  H01L23/00 ,  G11C11/4096 ,  G06F1/10 ,  G06F1/26 ,  G11C11/4093

Abstract: Disclosed is a memory device, which includes a buffer die that outputs a first power supply voltage to a first through-substrate via (e.g., through-silicon via (TSV)) and receives a small swing data signal from a second TSV generated based on the first power supply voltage, and a core die that is electrically connected to the buffer die through the first and second TSVs, includes a first cell capacitor electrically connected to the first TSV and configured to block a first noise introduced to the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

公开(公告)号：US11769547B2

公开(公告)日：2023-09-26

申请号：US17685067

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

IPC: G11C11/4076 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20210225426A1

公开(公告)日：2021-07-22

申请号：US17084345

申请日：2020-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

公开(公告)号：US20240249051A1

公开(公告)日：2024-07-25

申请号：US18449304

申请日：2023-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungoh Ahn ,  Jaewon Park

IPC: G06F30/327

CPC classification number: G06F30/327

Abstract: Disclosed is a memory device, which includes a logic circuit that receives a first signal and a second signal from an external host, an output circuit that receives a first logic operation result or a second logic operation result from the logic circuit, a first logic gate that receives the first signal or the second signal and performs a third logic operation to output a third signal, a second logic gate that receives the first signal and the second signal and performs a fourth logic operation to output a fourth signal, and a multiplexer that receives the third signal and the fourth signal, receives the first logic operation result or the second logic operation result from the output circuit, and outputs one of the third signal and the fourth signal as a fifth signal in response to the first or second logic operation results.

公开(公告)号：US11295808B2

公开(公告)日：2022-04-05

申请号：US17084345

申请日：2020-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

IPC: G11C11/4076 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  H01L25/18

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.