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公开(公告)号：US12176919B2
公开(公告)日：2024-12-24
申请号：US17988140
申请日：2022-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Kijun Lee , Myungkyu Lee , Sunghye Cho , Jin-Hoon Jang , Isak Hwang
Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.
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公开(公告)号：US20240005204A1
公开(公告)日：2024-01-04
申请号：US18054176
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiwon Lee , Sung-Rae Kim , Gilyoung Kang , Hye-Ran Kim , Chisung Oh
IPC: G06N20/00
CPC classification number: G06N20/00
Abstract: A semiconductor device includes a sequence data generator, which is configured to generate sequence data on a plurality of data lines, and a symbol changer. The symbol changer is configured to generate a training pattern from the sequence data by replacing, for each of the plurality of data lines, each occurrence of a bitstream within the sequence data that has a predetermined symbol with an alternative symbol. The sequence data generator may include a sequence generator, which is configured to generate a pseudo random binary sequence (PRBS), based on a seed value for each clock cycle.
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公开(公告)号：US10324785B2
公开(公告)日：2019-06-18
申请号：US15652521
申请日：2017-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Gyu Yeol Kong , Ki Jun Lee , Jun Jin Kong , Hong Rak Son , Beom Kyu Shin , Heon Hwa Cheong
Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.
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Patent Agency Ranking
公开(公告)号：US20250123920A1
公开(公告)日：2025-04-17
申请号：US18764870
申请日：2024-07-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yujung Song , Sung-Rae Kim , Hye-Ran Kim
IPC: G06F11/10
Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including a plurality of memory cells to store data, an error correction code (ECC) circuit, and an error check and scrub (ECS) circuit. The ECC circuit reads the data from the memory cell array and corrects errors in the data. The ECS circuit performs a scrubbing operation on the memory cell array and transmits a signal for an error address detected based on the scrubbing operation to an external circuit and stores the error address which was transmitted.
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公开(公告)号：US20250078947A1
公开(公告)日：2025-03-06
申请号：US18949589
申请日：2024-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US12205661B2
公开(公告)日：2025-01-21
申请号：US18093560
申请日：2023-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US11681458B2
公开(公告)日：2023-06-20
申请号：US17090726
申请日：2020-11-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kijun Lee , Sung-Rae Kim , Chanki Kim , Yeonggeol Song , Yesin Ryu , Jaeyoun Youn , Myungkyu Lee
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0673 , G06F11/1048 , G11C29/52
Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.
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公开(公告)号：US11551776B2
公开(公告)日：2023-01-10
申请号：US17392382
申请日：2021-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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