公开(公告)号：US10297078B2

公开(公告)日：2019-05-21

申请号：US15652610

申请日：2017-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-joon Yoo ,  Sundeep Krishnadasan ,  Soo-jung Ryu

IPC: G06T1/20 ,  G06T17/00 ,  G06T17/20 ,  G06T15/00 ,  G06T11/20

Abstract: Provided is a method of rendering a curve. The method includes determining a tessellation level of dividing a curve based on a control point of the curve, generating at least one triangle and at least two first sub-curves corresponding to the curve based on the tessellation level, and rendering the at least two first sub-curves and the at least one triangle.

公开(公告)号：US20180174351A1

公开(公告)日：2018-06-21

申请号：US15690999

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEON-GON CHO ,  Soo-jung Ryu

IPC: G06T15/00 ,  G06T15/80 ,  G06T15/04 ,  G06T15/50

CPC classification number: G06T15/005 ,  G06T15/04 ,  G06T15/503 ,  G06T15/80

Abstract: A method of processing a graphics pipeline in a graphics processing apparatus includes performing pixel shading to process pixels corresponding to an object, texturing the object, and transmitting data of a textured object to a processing path for a post-processing operation of the textured object. A graphics processing apparatus for processing a graphics pipeline includes a shading processor configured to perform pixel shading to process pixels corresponding to an object. A texturing processor is configured apply to texture the object, determine a post-processing operation mode to adjust visual effects of the textured object, and transmit data of the textured object to a processing path for the post-processing operation in accordance with the determined post-processing mode. A reorder buffer is configured to buffer data of the object in accordance with a processing order when the processing path bypasses the shading processor.

公开(公告)号：US09342480B2

公开(公告)日：2016-05-17

申请号：US14064497

申请日：2013-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Il-hyun Park

IPC: G06F9/30 ,  G06F15/82 ,  G06F9/38

CPC classification number: G06F15/82 ,  G06F9/30072 ,  G06F9/3853

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

公开(公告)号：US10055318B2

公开(公告)日：2018-08-21

申请号：US15681559

申请日：2017-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hoon Jeong ,  Ho-young Kim ,  Soo-jung Ryu

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/36

CPC classification number: G06F11/2236 ,  G06F11/263 ,  G06F11/3688

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

公开(公告)号：US09858116B2

公开(公告)日：2018-01-02

申请号：US14542827

申请日：2014-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-Gon Cho ,  Soo-jung Ryu

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/466

Abstract: A functional unit for supporting multithreading, a processor including the same, and an operating method of the processor are provided. The functional unit for supporting multithreading includes a plurality of input ports configured to receive opcodes and operands for a plurality of threads, wherein each of the plurality of input ports is configured to receive an opcode and an operand for a different thread, a plurality of operators configured to perform operations using the received operands, an operator selector configured to select, based on each opcode, an operator from among the plurality of operators to perform a specific operation using an operand from among the received operands, and a plurality of output ports configured to output operation results of operations for each thread.

公开(公告)号：US10311627B2

公开(公告)日：2019-06-04

申请号：US15690999

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-gon Cho ,  Soo-jung Ryu

IPC: G06T15/00 ,  G06T15/50 ,  G06T15/04 ,  G06T15/80

Abstract: A method of processing a graphics pipeline in a graphics processing apparatus includes performing pixel shading to process pixels corresponding to an object, texturing the object, and transmitting data of a textured object to a processing path for a post-processing operation of the textured object. A graphics processing apparatus for processing a graphics pipeline includes a shading processor configured to perform pixel shading to process pixels corresponding to an object. A texturing processor is configured apply to texture the object, determine a post-processing operation mode to adjust visual effects of the textured object, and transmit data of the textured object to a processing path for the post-processing operation in accordance with the determined post-processing mode. A reorder buffer is configured to buffer data of the object in accordance with a processing order when the processing path bypasses the shading processor.

公开(公告)号：US09772917B2

公开(公告)日：2017-09-26

申请号：US14259481

申请日：2014-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hoon Jeong ,  Ho-young Kim ,  Soo-jung Ryu

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/36

CPC classification number: G06F11/2236 ,  G06F11/263 ,  G06F11/3688

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

公开(公告)号：US20140052960A1

公开(公告)日：2014-02-20

申请号：US14064497

申请日：2013-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Il-hyun Park

IPC: G06F15/82

CPC classification number: G06F15/82 ,  G06F9/30072 ,  G06F9/3853

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Abstract translation: 本文提供了一种用于生成支持预定执行的非常长的指令字（VLIW）命令和用于处理VLIW的VLIW处理器和方法的装置和方法。 VLIW命令包括由并行执行的多个指令形成的指令束和指示预测执行的单个值，并且使用用于生成VLIW命令的装置和方法生成。 根据指示预先执行的值，VLIW处理器并行地解码指令束并且并行地执行包括在解码指令束中的指令。