公开(公告)号：US20170352434A1

公开(公告)日：2017-12-07

申请号：US15600715

申请日：2017-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min RYU ,  Hak-soo YU ,  Reum OH ,  Seong-young SEO ,  Soo-jung RHO

IPC: G11C29/12 ,  G11C5/00 ,  G11C29/26 ,  G11C29/54

CPC classification number: G11C29/12 ,  G11C5/005 ,  G11C5/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/46 ,  G11C29/54 ,  G11C2029/0409 ,  G11C2029/1208 ,  G11C2029/2602

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.