公开(公告)号：US20240222348A1

公开(公告)日：2024-07-04

申请号：US18238099

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol RYU ,  TAEHWAN KIM ,  SHLE-GE LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/48 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/48091 ,  H01L2224/48227

Abstract: A semiconductor package may include a first package including a first substrate, a first semiconductor chip mounted on the first substrate, and a second substrate on the first semiconductor chip, the first package having a center region, a first edge region surrounding the center region, and a second edge region surrounding the first edge region in a plan view, dummy balls disposed on the center region and the second edge region of the first package, connection terminals disposed on the first edge region of the first package, and a second package including a third substrate disposed on the dummy balls and the connection terminals and a second semiconductor chip mounted on the third substrate. The dummy balls may be in contact with the second substrate and may be spaced apart from the third substrate, and the connection terminals may be coupled to the second and third substrates.

公开(公告)号：US20240030185A1

公开(公告)日：2024-01-25

申请号：US18112107

申请日：2023-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-YOUN CHOI ,  Seunggeol RYU ,  YUN SEOK CHOI

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L23/5386

Abstract: A semiconductor package comprising a main semiconductor chip having a first thickness, at least one semiconductor device on one side of the main semiconductor chip and having a second thickness less than the first thickness, a first molding layer that covers the main semiconductor chip and the semiconductor device so as to expose a top surface of the semiconductor device and to expose a top surface and a portion of a lateral surface of the main semiconductor chip, a first redistribution substrate below the first molding layer, a second redistribution substrate on the first molding layer, and a mold via that penetrates the first molding layer and connects the first redistribution substrate to the second redistribution substrate.

公开(公告)号：US20230178450A1

公开(公告)日：2023-06-08

申请号：US17892252

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun JO ,  Jaemin JUNG ,  Jaechoon KIM ,  Seunggeol RYU ,  Kyungsuk OH

IPC: H01L23/367 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5283

Abstract: A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.