公开(公告)号：US20240324206A1

公开(公告)日：2024-09-26

申请号：US18581174

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungik YOO ,  Seungbeom KO ,  Taemok GWON ,  Changjin SON ,  Chadong YEO ,  Seulji LEE ,  Seungmin LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked; a channel structure passing through the mold structure in the memory cell region; a first cell contact passing through the mold structure in the connection region, connected to a first gate electrode and electrically disconnected from a second gate electrode; a plurality of support structures surrounding the first cell contact planarly in the connection region and extending through the mold structure; and a dam structure located between the first cell contact and the second gate electrode in the connection region and apart from the first cell contact with an insulating ring therebetween.

公开(公告)号：US20240222267A1

公开(公告)日：2024-07-04

申请号：US18396813

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungil LEE ,  Seungbeom KO ,  Jongyoon CHOI

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5226 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device comprising: a stack structure on a substrate including gate electrodes and insulating layers alternately stacked; a first through via extending through the stack structure; and a second through via spaced apart from the first through via, wherein the second through via extends through the stack structure, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the substrate in the vertical direction, wherein a gate pad is on and contacts the first gate electrode, and the first through via includes: a vertical pattern; first and second protrusions that protrude from the vertical pattern, wherein the first protrusion overlaps a portion of the first gate electrode in the horizontal direction; and the second protrusion overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is spaced apart from the second through via.