公开(公告)号：US20240194616A1

公开(公告)日：2024-06-13

申请号：US18514054

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Anthony Dongick LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/585 ,  H01L23/481 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：US20240258388A1

公开(公告)日：2024-08-01

申请号：US18537546

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Anthony Dongick LEE ,  Minseung LEE ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.

公开(公告)号：US20250098264A1

公开(公告)日：2025-03-20

申请号：US18604031

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheol NA ,  Beomjin KIM ,  Yoolim AHN ,  Kyoungwoo LEE ,  Minseung LEE ,  Hyeryeong LEE ,  Keun Hwi CHO ,  Seungseok HA

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

公开(公告)号：US20230065281A1

公开(公告)日：2023-03-02

申请号：US17751819

申请日：2022-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Sungyup JUNG ,  Youngwoo CHO

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device including a first insulating structure on a substrate and including a first etch stop layer and a first interlayer insulating layer on the first etch stop layer, a second insulating structure on the first insulating structure and including a second etch stop layer and a second interlayer insulating layer on the second etch stop layer, a conductive line penetrating through the second insulating structure, and extending in a first direction parallel to an upper surface of the substrate, and a plurality of contacts penetrating through the first insulating structure and connected to the conductive line may be provided. The conductive line may include a protrusion extending below the second insulating structure and penetrating through the first interlayer insulating layer to be in contact with the first etch stop layer.