公开(公告)号：US20150048512A1

公开(公告)日：2015-02-19

申请号：US14273272

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Gu KANG ,  OhKyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

Abstract translation: 通过在包括第一和第二区域的基板上形成下部结构来制造半导体器件，同时在第一区域的下部结构上形成第一互连和在第二区域的下部结构上形成第二互连的第一部分，形成 在所述第一互连上和所述第二互连的所述第一部分上的第一层间绝缘层，形成在所述第一层间绝缘层中露出所述第二互连的第一部分的顶表面的沟槽，以及形成所述第二互连的第二部分 在沟里。 还公开了相关结构。

公开(公告)号：US09299659B2

公开(公告)日：2016-03-29

申请号：US14273272

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Gu Kang ,  OhKyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

Abstract translation: 通过在包括第一和第二区域的基板上形成下部结构来制造半导体器件，同时在第一区域的下部结构上形成第一互连和在第二区域的下部结构上形成第二互连的第一部分，形成 在所述第一互连上和所述第二互连的所述第一部分上的第一层间绝缘层，形成在所述第一层间绝缘层中露出所述第二互连的第一部分的顶表面的沟槽，以及形成所述第二互连的第二部分 在沟里。 还公开了相关结构。