公开(公告)号：US20250068225A1

公开(公告)日：2025-02-27

申请号：US18947457

申请日：2024-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee YOO ,  Jaehyun KIM ,  Jingyu AHN ,  Wooil KIM ,  Manhwee JO

IPC: G06F1/3234 ,  G11C7/22

Abstract: A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

公开(公告)号：US20230184830A1

公开(公告)日：2023-06-15

申请号：US17988989

申请日：2022-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwook KIM ,  Heeseong LEE ,  Myonghoon YANG ,  Manhwee JO ,  Wooil KIM

IPC: G01R31/317

CPC classification number: G01R31/31718 ,  G01R31/31723 ,  G01R31/31712

Abstract: A system of monitoring performance of an electronic device including: a plurality of performance monitoring circuits included in an electronic device, wherein the plurality of performance monitoring circuits are configured to generate a plurality of monitor output signals including performance data of the electronic device; a monitoring bus configured to receive the plurality of monitor output signals and generate a. bus output signal by interleaving the performance data included in the plurality of monitor output signals; and an embedded trace router configured to receive the bus output signal and store, in a memory device included in the electronic device, the performance data. included in the bus output signal,