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    SEMICONDUCTOR DEVICE HAVING SUPPORTERS AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SUPPORTERS AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有支持者的半导体器件及其制造方法

    公开(公告)号：US20170077102A1

    公开(公告)日：2017-03-16

    申请号：US15083819

    申请日：2016-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/45 ,  H01L23/522

    CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

    Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

    Abstract translation: 半导体器件包括衬底上的存储电极和被配置为耦合存储电极的一个或多个部分的一个或多个支撑器。 半导体器件可以包括平行于衬底的表面延伸的多个不相交的支撑体。 至少一个支撑件可以具有与存储电极的上表面基本上共面的上表面。 存储电极可以包括保形地覆盖存储电极的一个或多个表面和一个或多个支持者的电容器电介质层。 存储电极可以包括耦合在一起的上部和下部存储电极。 上下存储电极可以具有不同的水平宽度。

    SEMICONDUCTOR DEVICES HAVING AIR SPACERS AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES HAVING AIR SPACERS AND METHODS OF MANUFACTURING THE SAME 有权
    具有空气间隔的半导体器件及其制造方法

    公开(公告)号：US20170062347A1

    公开(公告)日：2017-03-02

    申请号：US15095327

    申请日：2016-04-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

    IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108

    CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

    Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

    Abstract translation: 半导体器件包括在衬底上彼此间隔开的第一和第二位线结构，部分地填充在第一和第二位线结构之间的通孔插头，与通孔插头的上表面接触的通孔焊盘和上部 第一位线结构的侧壁，通孔焊盘与第二位线结构的上部间隔开，填充有通孔插塞和第一位线结构之间的空气的第一腔体和填充有空气的第二腔体， 所述通孔插头和所述第二位线结构。具有位于所述第一位线结构的上侧壁上的第一部分的间隙封盖间隔件以及覆盖所述第一空气间隔件的第二部分。 第一部分的水平宽度小于第二部分的水平宽度。

    SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20140203377A1

    公开(公告)日：2014-07-24

    申请号：US14161867

    申请日：2014-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Seung SONG ,  Kyung-Eun KIM ,  Jae-Kyun PARK

    IPC: H01L27/02

    CPC classification number: H01L27/0207 ,  H01L27/1104 ,  H01L2027/11812 ,  H01L2027/11838

    Abstract: Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices.

    Abstract translation: 半导体器件包括设置在第一有源区上的第一栅极图案，第一有源区上的第二栅极图案，第二有源区上的第三栅极图案，以及第二有源区上的第四栅极图案。 第二栅极图案在第一方向上平行于第一栅极图案。 第三栅极图案相对于第一方向具有与第一栅极图案不对称的形状，并且第四栅极图案在第一方向上平行于第三栅极图案，并且相对于第二栅极图案具有与第二栅极图案不对称的形状 第一个方向。 可以在窄的水平区域中提供具有良好性能的MOS晶体管。 MOS晶体管可以用于高度堆叠的半导体器件中。

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