公开(公告)号：US20220157822A1

公开(公告)日：2022-05-19

申请号：US17392775

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung AHN ,  Yongseok AHN ,  Hyunyong KIM ,  Minsub UM ,  Ju Hyung WE ,  Joonkyu RHEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

公开(公告)号：US20220165608A1

公开(公告)日：2022-05-26

申请号：US17574665

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun IM ,  Kibum LEE ,  Daehyun KIM ,  Ju Hyung WE ,  Sungmi YOON

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/02 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/146 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.