公开(公告)号：US09076928B2

公开(公告)日：2015-07-07

申请号：US13906044

申请日：2013-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Seok Yang ,  Ki Seok Kim ,  Je Won Kim ,  Ju Bin Seo ,  Sang Seok Lee ,  Joon Sub Lee ,  Jin Bock Lee

IPC: H01L33/00 ,  H01L33/36 ,  H01L33/02 ,  H01L27/15

CPC classification number: H01L33/36 ,  H01L27/15 ,  H01L33/02

Abstract: A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively.

Abstract translation: 提供了半导体发光器件，并且包括具有第一下导电型半导体层和第二下导电型半导体层的保护元件。 第一和第二下电极分别连接到第一下导电型半导体层和第二下导电型半导体层。 发光结构包括依次形成在保护元件上的第一上导电型半导体层，有源层和第二上导电型半导体层。 第一上电极和第二上电极分别连接到第一上导电型半导体层和第二上导电型半导体层。

公开(公告)号：US12170259B2

公开(公告)日：2024-12-17

申请号：US17715103

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Bin Seo ,  Seok Ho Kim ,  Kwang Jin Moon

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

公开(公告)号：US20240006362A1

公开(公告)日：2024-01-04

申请号：US18155988

申请日：2023-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Bin Seo ,  Seok Ho Kim ,  Kwang Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/14519 ,  H01L2224/1403 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/13083 ,  H01L2224/05655 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13144

Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.

公开(公告)号：US09461205B2

公开(公告)日：2016-10-04

申请号：US14338174

申请日：2014-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Goo Cha ,  Hyun Seong Kum ,  Ju Bin Seo ,  Dong Hoon Lee

IPC: H01L27/15 ,  H01L33/24 ,  H01L33/18 ,  H01L33/08

CPC classification number: H01L33/24 ,  H01L33/08 ,  H01L33/18 ,  H01L33/385

Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer and a plurality of light emitting nanostructures. The base layer is formed of a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. Each of the light emitting nanostructures is disposed on the exposed regions of the base layer and includes nanocore formed of a first conductivity type semiconductor, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on side surfaces of the nanocore. Upper surfaces of the light emitting nanostructures are non-planar and contain portions free of the second conductivity-type semiconductor layer in order to prevent light emissions during device driving.

Abstract translation: 纳米结构半导体发光器件包括基底层，绝缘层和多个发光纳米结构。 基层由第一导电型半导体形成。 绝缘层设置在基底层上并具有多个开口，基底层的区域暴露在该开口中。 每个发光纳米结构设置在基底层的暴露区域上，并且包括由第一导电型半导体形成的纳米孔，以及顺序地设置在纳米孔的侧表面上的有源层和第二导电类型半导体层。 发光纳米结构的上表面是非平面的，并且包含不含第二导电型半导体层的部分，以便防止器件驱动期间的光发射。