公开(公告)号：US20210026249A1

公开(公告)日：2021-01-28

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  G05B19/4097 ,  H01L21/027

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US12072637B2

公开(公告)日：2024-08-27

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/00 ,  G05B19/4097 ,  H01L21/027

CPC classification number: G03F7/705 ,  G05B19/4097 ,  H01L21/0273 ,  G05B2219/45028

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US20230047588A1

公开(公告)日：2023-02-16

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US11493850B2

公开(公告)日：2022-11-08

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.