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    ELECTRONIC DEVICE, METHOD, AND COMPUTER-READABLE STORAGE MEDIUM FOR REDUCING AFTERIMAGE IN DISPLAY AREA
    1.
    发明申请
    ELECTRONIC DEVICE, METHOD, AND COMPUTER-READABLE STORAGE MEDIUM FOR REDUCING AFTERIMAGE IN DISPLAY AREA 有权

    公开(公告)号：US20220415226A1

    公开(公告)日：2022-12-29

    申请号：US17733547

    申请日：2022-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinhyun KIM ,  Jaesung LEE ,  Hanyuool KIM ,  Jongkon BAE ,  Yohan LEE ,  Seungkyu CHOI

    IPC: G09G3/00 ,  H05K5/00

    Abstract: An electronic device is provided. The electronic device includes a housing, a display rollable into the housing, and a display driver circuitry operably coupled to the display. The display driver circuitry is configured to display, while the electronic device is in a first state in which a first display area of the display is exposed and a second display area of the display adjacent to the first display area is rolled into the housing, a first image in the exposed first display area, obtain, a second image based on applying a first weight to a pixel value of a first pixel of a first horizontal line and applying a second weight less than the first weight to a pixel value of a second pixel of the first horizontal line, and display, while displaying the first image, the second image in the second display area rolled into the housing.

    ELECTRONIC DEVICE FOR APPLYING EFFECT FOR MOVING OBJECT TO IMAGE AND METHOD FOR OPERATING THE SAME
    2.
    发明申请
    ELECTRONIC DEVICE FOR APPLYING EFFECT FOR MOVING OBJECT TO IMAGE AND METHOD FOR OPERATING THE SAME 有权

    公开(公告)号：US20220385832A1

    公开(公告)日：2022-12-01

    申请号：US17674236

    申请日：2022-02-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Inkoo KANG ,  Sungoh KIM ,  Jinhyun KIM ,  Jonghoon WON ,  Sangjun YU

    IPC: H04N5/265 ,  H04N5/225 ,  G06T7/12 ,  H04N5/262 ,  H04N5/232 ,  G06T7/246

    Abstract: According to various embodiments, an electronic device is provided. The electronic device includes a display, a RGB sensor including a plurality of first pixels, a dynamic vision sensor including a plurality of second pixels, and a processor electrically connected with the display, the RGB sensor, and the dynamic vision sensor. The processor may be configured to detect a first signal to request to capture an image, obtain a first image including a first object using the RGB sensor, based on the detection of the first signal, identify at least one edge of the first object corresponding to at least one second image obtained during a first period specified by a time of detecting the first signal, among a plurality of second images obtained using the dynamic vision sensor, generate a synthesized image in which an effect related to the at least one edge of the first object is applied to the first image, and control the display to display the synthesized image.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20240422976A1

    公开(公告)日：2024-12-19

    申请号：US18656694

    申请日：2024-05-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyoung KIM ,  Jinhyun KIM

    IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

    Abstract: A semiconductor device including gate electrodes stacked and spaced apart from each other in a first direction, extending by different lengths in a second direction on the second region, and each including a pad region having an upper surface exposed upwardly in the second region and a stack region other than the pad region, the gate electrodes including a first gate electrode and a second gate electrode below the first gate electrode, a first contact plug insulating layer on interlayer insulating layers in the pad region of the first gate electrode, surrounding a gate contact plug, and vertically overlapping the first gate electrode, second contact plug insulating layers alternating with the interlayer insulating layers below the pad region of the first gate electrode and surrounding the gate contact plug may be provided.

    TRANSFORMER FOR LOW LOSS AND APPARATUS INCLUDING THE SAME
    9.
    发明申请
    TRANSFORMER FOR LOW LOSS AND APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20230031672A1

    公开(公告)日：2023-02-02

    申请号：US17963693

    申请日：2022-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kihyun KIM ,  Sangho LEE ,  Jinhyun KIM ,  Hyunchul PARK

    IPC: H03F1/56 ,  H03F3/195

    Abstract: The disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system, such as long term evolution (LTE). A transformer is provided. The transformer includes a first primary inductor, a second primary inductor, and a secondary inductor. The secondary inductor may be disposed between the first primary inductor and the second primary inductor. The secondary inductor may be disposed spaced apart from the first primary inductor and the second primary inductor.

    INTELLIGENT HIGH BANDWIDTH MEMORY APPLIANCE
    10.
    发明申请
    INTELLIGENT HIGH BANDWIDTH MEMORY APPLIANCE 审中-公开

    公开(公告)号：US20190050325A1

    公开(公告)日：2019-02-14

    申请号：US15796743

    申请日：2017-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN ,  Hyungseuk KIM ,  Jinhyun KIM

    IPC: G06F12/02 ,  G06F12/0862

    Abstract: Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.

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