公开(公告)号：US20240222123A1

公开(公告)日：2024-07-04

申请号：US18356322

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang In KIM ,  Si Nyeon KIM ,  Jiho PARK ,  Youngwoo SON ,  Ji-Eun LEE ,  Young-Seung CHO

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device may include forming an active pattern on a substrate, sequentially forming on the substrate a base mask, a first mask layer, a first capping layer, a second mask layer, a second capping layer, a third mask layer, a third capping layer, a fourth mask layer, and a fourth capping layer, forming first spacers, forming second spacers, forming third spacers, and using the third spacers as a mask to pattern the first mask layer and the first capping layer. Forming the third spacers may include forming a spacer layer to completely fill a space between the sidewalls of patterns of the patterned second mask layer.

公开(公告)号：US20240071771A1

公开(公告)日：2024-02-29

申请号：US18355520

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo KIM ,  Yonghan PARK ,  Jiho PARK ,  Geumjung SEONG ,  Seunguk HAN

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/3086

Abstract: A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

公开(公告)号：US20250164872A1

公开(公告)日：2025-05-22

申请号：US18774118

申请日：2024-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho PARK ,  Hun KIM ,  Sora PARK ,  Hyungkeun YOO ,  Younghun KWON ,  Jongchul KIM ,  Jaeyoung YANG ,  Chihoon LEE

IPC: G03F1/84 ,  G03F7/20 ,  G06T7/00 ,  G06T7/60

Abstract: A semiconductor structure inspection method includes obtaining an image of a semiconductor structure, the semiconductor structure including a wafer, a semiconductor layer, and an inspection pattern, determining a material of an insertion layer to be inserted in the semiconductor structure, determining a thickness of the insertion layer, inserting the insertion layer having the determined material and the determined thickness in the semiconductor structure, and measuring the semiconductor structure having the insertion layer inserted therein.

公开(公告)号：US20250057049A1

公开(公告)日：2025-02-13

申请号：US18928893

申请日：2024-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho PARK

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

公开(公告)号：US20240381623A1

公开(公告)日：2024-11-14

申请号：US18412858

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungha LEE ,  Jiho PARK ,  Seok-Won KIM ,  Sanghyeok YU

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate; a bit line disposed on the substrate and extending in a first direction; a first interlayer insulating layer disposed on the bit line, and including a channel trench extending in a second direction crossing the first direction; a second interlayer insulating layer disposed on the first interlayer insulating layer; a channel pattern disposed in the channel trench; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern disposed between the channel pattern and the word line; an insulating pattern disposed on the word line; and a landing pad connected to the channel pattern. The landing pad includes a first protrusion disposed between the channel pattern and the second interlayer insulating layer, and a second protrusion disposed between the channel pattern and the insulating pattern.

公开(公告)号：US20220123205A1

公开(公告)日：2022-04-21

申请号：US17314320

申请日：2021-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho PARK

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.