公开(公告)号：US09064603B1

公开(公告)日：2015-06-23

申请号：US14185302

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn Youn ,  Su-A Kim ,  Hyo-Jin Choi ,  Chul-Woo Park ,  Hak-Soo Yu

IPC: G11C7/10 ,  G11C11/409

CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

Abstract translation: 半导体存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括第一和第二子阵列，第一子阵列包括第一组阵列阵列，而第二子阵列包括第二组阵列阵列。 上部和下部排列阵列中的每一个包括相对于彼此具有不同定时参数的第一和第二部分。 控制逻辑控制对第一和第二部分的访问，使得在第一和第二部分上执行读/写操作。

公开(公告)号：US09318168B2

公开(公告)日：2016-04-19

申请号：US14090510

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo Park ,  Dong-Soo Kang ,  Su-A Kim ,  Jun-hee Yoo ,  Hak-Soo Yu ,  Jae-Youn Youn ,  Sung-hyun Lee ,  Kyoung-Heon Jeong ,  Hyo-Jin Choi ,  Young-Soo Sohn

IPC: G06F12/02 ,  G11C7/10 ,  G11C29/00

CPC classification number: G11C7/1072 ,  G06F12/0223 ,  G06F12/0292 ,  G11C29/76 ,  G11C29/84

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract translation: 在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。 配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。 存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。