Abstract:
In one embodiment, an image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter configured to convert analog pixel signals output from the pixels into digital signals, a first cluster configured to store a first group of digital signals among the digital signals and to output first image data, a second cluster configured to store a second group of digital signals among the digital signals and to output second image data, and at least one cluster switch connected to the first cluster and the second cluster, a first channel, and a second channel. The image sensor is configured to transmit at least one among the first image data and the second image data to at least one among the first channel and the second channel based on an operation mode.
Abstract:
An image sensor includes a comparator configured to compare a pixel signal with a ramp signal and generate a comparison signal and a counter configured to be reset by a counter reset value based on an offset of the comparator and to generate a digital pixel signal according to the comparison signal.
Abstract:
An image sensor includes a pixel including a reset circuit and a floating diffusion node, and outputting a pixel signal that is generated based on a voltage at the floating diffusion node, the pixel signal including a reset output that is generated based on the voltage at the floating diffusion node being reset by the reset circuit. The image sensor further includes a sampler sampling the output pixel signal to generate a sampling signal having a time interval corresponding to a magnitude of the output pixel signal, and a counter counting the generated sampling signal, based on a counter clock, to generate a counting value corresponding to the time interval of the sampling signal. The sampler samples the reset output of the output pixel signal n times to generate first to n-th reset sampling signals, where n is an integer of 2 or more.
Abstract:
An image sensor including a comparator configured to generate a comparison signal by comparing a ramp signal and a pixel signal with each other, a counter configured to generate a digital pixel value by counting an input clock signal according to the comparison signal, and a divider configured to control a frequency of the input clock signal according to an analog gain of the image sensor.
Abstract:
An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
Abstract:
Disclosed are an image sensor having a light-emitting diode (LED) flicker mitigation function and an image processing system including the image sensor. The image processing system includes an image sensor including a plurality of pixels, the plurality of pixels configured to respectively generate pixel signals corresponding to photocharges, and configured to perform analog-to-digital conversion (ADC) on the pixel signals to generate digital pixel signals; and an image signal processor configured to process the digital pixel signals to generate image data. The image sensor operates in a first operating mode in a situation in which a light-emitting diode (LED) light is provided, and operates in a second operating mode in a general situation in which the LED light is not provided.
Abstract:
A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.