公开(公告)号：US20170256544A1

公开(公告)日：2017-09-07

申请号：US15351673

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Suk CHAI ,  Hu Yong LEE ,  Sang Yong KIM ,  Taek Soo JEON ,  Won Keun CHUNG ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain regions, a first semiconductor layer between the first source/drain regions, a first gate electrode structure, and a first gate dielectric structure; and a second MOS transistor including second source/drain regions, a second semiconductor layer between the second source/drain regions, a second gate electrode structure, and a second gate dielectric structure. The first gate dielectric structure and the second gate dielectric structure include a first common dielectric structure; the first gate dielectric structure includes a first upper dielectric on the first common dielectric structure; the second gate dielectric structure includes the first upper dielectric and a second upper dielectric; and one of the first upper dielectric and the second upper dielectric is a material forming a dipole layer.

公开(公告)号：US20180261677A1

公开(公告)日：2018-09-13

申请号：US15653588

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon LEE ,  Hyeon Jin KIM ,  Hoon Joo NA ,  Sung In SUH ,  Chan Hyeong LEE ,  Hu Yong LEE ,  Seong Hoon JEONG ,  Sang Jin HYUN

IPC: H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L21/28

Abstract: A semiconductor device includes a gate insulating layer disposed on a substrate, a first work function tuning layer disposed on the gate insulating layer, a lower barrier conductive layer on and in contact with the first work function tuning layer, and an upper barrier conductive layer on and in contact with the lower barrier conductive layer. The upper barrier conductive layer and the lower barrier conductive layer include a material in common, e.g., they may each include a titanium nitride (TiN) layer.