公开(公告)号：US10685977B2

公开(公告)日：2020-06-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US10608091B2

公开(公告)日：2020-03-31

申请号：US16121020

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Wan Lim ,  Hojong Kang ,  Joowon Park

IPC: H01L23/52 ,  H01L29/423 ,  H01L23/31 ,  H01L27/11582 ,  H01L21/28 ,  H01L23/485 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11575 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

公开(公告)号：US10186519B2

公开(公告)日：2019-01-22

申请号：US15059993

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US20190019872A1

公开(公告)日：2019-01-17

申请号：US16121020

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Wan LIM ,  Hojong Kang ,  Joowon Park

IPC: H01L29/423 ,  H01L21/28 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11575 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792 ,  H01L23/31 ,  H01L27/11582 ,  H01L23/485

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.