公开(公告)号：US20180122434A1

公开(公告)日：2018-05-03

申请号：US15792973

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Geun LEE ,  Young Jin CHO ,  Hee Hyun NAM ,  Hyo Deok SHIN ,  Young Kwang YOO

IPC: G11C7/10 ,  G06F13/16 ,  G11C8/06 ,  G06F12/0879

CPC classification number: G11C7/1057 ,  G06F12/0879 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/106 ,  G11C7/1066 ,  G11C8/06 ,  G11C8/12 ,  G11C2207/2254

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

公开(公告)号：US20250147690A1

公开(公告)日：2025-05-08

申请号：US18743963

申请日：2024-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-suk MOON ,  Bokyoung KIM ,  Hee Hyun NAM ,  Jinwoo SONG ,  Hyewon JEONG

IPC: G06F3/06

Abstract: An operating method of a storage device includes fetching, from an external host device, write command and write data, based on a 0-th fetch rate, storing the write data in a write cache region of a buffer memory device of the storage device, performing write cache processing with respect to the write cache region, based on a 0-th cache processing rate, the performing write cache processing including storing, in a nonvolatile memory device of the storage device, the write data of the write cache region, detecting a write cache level of the write cache region, and controlling the 0-th cache processing rate, based on the write cache level.

公开(公告)号：US20220068424A1

公开(公告)日：2022-03-03

申请号：US17318234

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho LEE ,  Kwangjin LEE ,  Hee Hyun NAM ,  Jaeho SHIN ,  Youngkwang YOO

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.

公开(公告)号：US20190303045A1

公开(公告)日：2019-10-03

申请号：US16443551

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Hee Hyun NAM ,  Hyo-Deok SHIN ,  Junghwan RYU

IPC: G06F3/06 ,  G11C16/10

Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.