公开(公告)号：US20170213842A1

公开(公告)日：2017-07-27

申请号：US15067855

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-chul PARK ,  Bio KIM ,  Young-Gu KIM ,  Jaehoon JEONG ,  Eunsuk CHO ,  Hyejin CHO ,  Jong In YUN

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117

Abstract: A semiconductor memory device includes a substrate, a stack disposed on the substrate, a vertical channel structure penetrating the stack, and a fixed charge layer disposed in the vertical channel structure. The stack includes insulating patterns and gate electrodes alternately and repeatedly disposed on one another. The vertical channel structure includes a data storing pattern.

公开(公告)号：US20200312862A1

公开(公告)日：2020-10-01

申请号：US16902575

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Eunsuk CHO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/11575

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

公开(公告)号：US20240365543A1

公开(公告)日：2024-10-31

申请号：US18435328

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegon LEE ,  Minkyu KANG ,  Sungjun KIM ,  Woongseop LEE ,  Eunsuk CHO ,  Jongyoon CHOI ,  Hyungyu HWANG

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H10B80/00

Abstract: A semiconductor device comprising; a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines on the circuit elements; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes, a plate layer, a plurality of gate electrodes spaced apart from each other and stacked on the plate layer in a first direction, perpendicular to an upper surface of the plate layer, the gate electrodes including a lower select gate electrode, memory gate electrodes, and an upper select gate electrode sequentially stacked, channel structures passing through the lower select gate electrode and the memory gate electrodes and extending in the first direction, stud structures passing through the upper select gate electrode and respectively connected to the channel structures.

公开(公告)号：US20210391349A1

公开(公告)日：2021-12-16

申请号：US17460814

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Eunsuk CHO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/11575

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

公开(公告)号：US20180358371A1

公开(公告)日：2018-12-13

申请号：US15982001

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Eunsuk CHO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/423

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.