公开(公告)号：US20210118890A1

公开(公告)日：2021-04-22

申请号：US17137684

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US20210296237A1

公开(公告)日：2021-09-23

申请号：US17097337

申请日：2020-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

公开(公告)号：US20200083229A1

公开(公告)日：2020-03-12

申请号：US16520730

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4091

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US20220037317A1

公开(公告)日：2022-02-03

申请号：US17451688

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BEOMJIN PARK ,  DONGIL BAE ,  DAEWON KIM ,  TAEYOUNG KIM ,  JOOHEE JUNG ,  JAEHOON SHIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.