公开(公告)号：US09047929B2

公开(公告)日：2015-06-02

申请号：US13967506

申请日：2013-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsung Seo ,  Chul-Sung Park ,  Chi-Sung Oh

IPC: G11C29/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02

CPC classification number: G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/22

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract translation: 存储器装置包括共享输入/输出线的至少两个存储器等级，至少一个模式寄存器，被配置为存储用于调整通过输入/输出线输出的至少两个等级的数据信号延迟的位;控制器，被配置为确定 基于所述至少一个模式寄存器中存储的比特来调整所述数据信号的参数，所述调整参数至少包括所述数据信号的延迟，以及至少一个非易失性存储器，其被布置在所述至少两个存储器排中的至少一个中 并且被配置为存储调谐参数。

公开(公告)号：US09436545B2

公开(公告)日：2016-09-06

申请号：US14165820

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Sung Oh ,  Chul-Sung Park ,  Sang-Bo Lee ,  Dong-Hyun Sohn

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G11C11/00 ,  G11C29/42 ,  G11C29/44 ,  G11C11/4076 ,  G11C11/40 ,  G11C29/04 ,  G11C29/12

CPC classification number: G06F11/1048 ,  G06F11/16 ,  G11C11/005 ,  G11C11/40 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract translation: 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

公开(公告)号：US09135981B2

公开(公告)日：2015-09-15

申请号：US14692797

申请日：2015-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsung Seo ,  Chul-Sung Park ,  Chi-Sung Oh

IPC: G11C29/22 ,  G11C11/4076 ,  G11C17/16 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/22

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.