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公开(公告)号：US20240081075A1
公开(公告)日：2024-03-07
申请号：US18131924
申请日：2023-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byongju KIM , Dongsung CHOI , Wonjun PARK , Donghwa LEE , Jaemin JUNG , Changheon CHEON
IPC: H10B43/40 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC classification number: H10B43/40 , H01L23/5283 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
Abstract: A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.
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公开(公告)号：US20240090220A1
公开(公告)日：2024-03-14
申请号：US18367619
申请日：2023-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaemin JUNG , Byongju KIM , Wonjun PARK , Donghwa LEE , Changheon CHEON , Dongsung CHOI
IPC: H10B43/27 , G11C5/06 , G11C16/04 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40 , H10B80/00
CPC classification number: H10B43/27 , G11C5/063 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor device includes a plurality of gate electrodes spaced apart from each other in a vertical direction on a substrate, a plurality of channel structures respectively penetrating a plurality of gate electrodes and extending in the vertical direction, each comprising a channel layer having a stacked structure of a first oxide semiconductor channel layer and a second oxide semiconductor channel layer which have different conductivities, and a gate insulating layer disposed between the channel layer and each of the plurality of gate electrodes, and a plurality of bit lines disposed on the plurality of channel structures and respectively connected to the plurality of channel structures, and the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed.
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公开(公告)号：US20240196618A1
公开(公告)日：2024-06-13
申请号：US18528970
申请日：2023-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju KIM , Dongsung CHOI , Wonjun PARK , Donghwa LEE , Jaemin JUNG , Changheon CHEON
Abstract: An integrated circuit device includes a semiconductor substrate; a plurality of conductive lines extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure passing through the plurality of conductive lines and the plurality of insulating layers, wherein the channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, a gate insulating layer on an outer wall of the channel layer, and a ferroelectric layer on an outer wall of the gate insulating layer.
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