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公开(公告)号:US20250081514A1
公开(公告)日:2025-03-06
申请号:US18650251
申请日:2024-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gyuhwan Oh , Seokhan Park , Bowon Yoo , Jinwoo Han
Abstract: A semiconductor device includes a back gate line that is on a substrate and extends in a first direction, a plurality of channel structures that are on side walls of the back gate line and spaced apart from each other in a second first direction that intersects the first direction, a word line that at least partially surrounds the plurality of channel structures, and a bit line on a lower surface of each of the plurality of channel structures, where each of the plurality of channel structures includes: a first side wall facing the word line, and a second side wall that faces the back gate line and contacts an edge of the first side wall, where the first side wall is curved, and where the second side wall is flat.
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公开(公告)号:US20230345696A1
公开(公告)日:2023-10-26
申请号:US18132198
申请日:2023-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhan Park , Bowon Yoo , Hyunseo Shin , Kiseok Lee , Moonyoung Jeong
IPC: H10B12/00
CPC classification number: H10B12/0387 , H10B12/0383 , H10B12/488
Abstract: A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate. A plurality of first filling layers is formed that fills the first trenches and have protrusions extending to protrude from the substrate. Spacers are formed on sidewalls of the protrusions of the first filling layers. The spacers expose portions of the substrate between adjacent first filling layers. A plurality of second trenches is formed around the first trenches by etching the portions of the substrate exposed by the spacers. A plurality of second filling layers is formed that fills the second trenches. All of the first filling layers and the spacers are removed. A gate material layer is formed that conformally covers inner walls of the first trenches. A pair of gate structures is formed in each of the first trenches by separating the gate material layer.
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