公开(公告)号：US20160078957A1

公开(公告)日：2016-03-17

申请号：US14660648

申请日：2015-03-17

Applicant: Samsung Display Co., Ltd.

Inventor： Yun Mi KIM ,  Ki Hyun PYUN ,  Sung Jun KIM ,  Min Young PARK ,  Jeong Doo LEE ,  Kyung Hwa LIM

IPC: G11C16/28 ,  G09G5/395 ,  H03M1/66 ,  G11C16/10 ,  G11C16/26

CPC classification number: G09G5/395 ,  G09G3/3648 ,  G09G5/12 ,  G09G5/393 ,  G09G2330/021 ,  G09G2360/12 ,  G11C7/16 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H03M1/66

Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Abstract translation: 提供了一种存储器，其包括电可擦除和可编程只读存储器（EEPROM），其被配置为存储操作系统并且响应于写入操作信号可重写，地址比较器被配置为连接到内部集成电路（I2C） 线路，并响应于外部信号将写入操作信号输出到EEPROM;数模转换器（DAC）单元，被配置为响应于外部信号确定是否连接DAC电阻器和I2C线路 - 配置为连接到I2C线路的电阻单元。

公开(公告)号：US20150091883A1

公开(公告)日：2015-04-02

申请号：US14161521

申请日：2014-01-22

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Yun Mi KIM ,  Min Young PARK ,  Sung-Jun KIM ,  Ju Hyun KIM ,  Yong Jae LEE ,  Kyung-Hwa LIM

IPC: G09G3/34

CPC classification number: G09G3/2074 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2320/0252

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract translation: 公开了一种减少将具有多个栅极线的显示装置的栅极线驱动信号从小于全栅极导通电平的电平切换到栅极导通电平的方法。 该方法可以包括：在相应栅极线的栅极线预充电周期期间，使栅极线驱动信号处于完全栅极导通电平; 在预充电周期之后的相应的栅极线主充电期间，使栅极线驱动信号处于全栅极导通电平; 并且在插入在栅极线预充电周期与其对应的栅极线主充电周期之间的插入时段期间，使栅极线驱动信号处于处于完全栅极导通电平之间的中间电平， 关门水平