公开(公告)号：US20150140699A1

公开(公告)日：2015-05-21

申请号：US14455805

申请日：2014-08-08

Applicant: Samsung Display Co., Ltd. ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Yeon-Hong Kim ,  Byung-Du AHN ,  Hyeon-Sik KIM ,  Yeon-Gon MO ,  Ji-Hun LIM ,  Hyun-Jae KIM

IPC: H01L21/02 ,  H01L51/56

CPC classification number: H01L21/02664 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L2227/323

Abstract: A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided. An oxide semiconductor device may be formed over the first major surface to provide an intermediate device, and the semiconductor device may comprise an oxide active layer. The intermediate device may be subjected to ultraviolet (UV) light (e.g., ultraviolet ray irradiation process) for a first period, and subjected to heat (e.g., thermal treatment process) for a second period. The first and second periods may at least partly overlap.

Abstract translation: 可以提供形成氧化物半导体器件的方法。 在该方法中，可以提供包括第一主表面和远离第一主表面的第二主表面的基板。 可以在第一主表面上形成氧化物半导体器件以提供中间器件，并且半导体器件可以包括氧化物有源层。 中间装置可以经受第一阶段的紫外线（UV）光（例如紫外线照射处理），并进行第二时段的加热（例如热处理）。 第一和第二周期可以至少部分重叠。

公开(公告)号：US09583633B2

公开(公告)日：2017-02-28

申请号：US14392369

申请日：2014-02-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du Ahn ,  Gun Hee Kim ,  Yeon-Hong Kim ,  Jin Hyun Park ,  Shuji Kosaka ,  Kazushi Hayashi

IPC: H01L29/10 ,  H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/66969

Abstract: In an oxide for a semiconductor layer of a thin film transistor according to the present invention, wherein metal elements constituting the oxide are In, Zn, and Sn, an oxygen partial pressure is 15% by volume or more when depositing the oxide in the semiconductor layer of the thin film transistor, and a defect density of the oxide satisfies 7.5×1015cm−3 or less, and a mobility satisfies 15 cm2/Vs or more.

Abstract translation: 在本发明的薄膜晶体管用半导体层用氧化物中，构成氧化物的金属元素为In，Zn，Sn，在半导体中沉积氧化物时的氧分压为15体积％以上 薄膜晶体管的层，氧化物的缺陷密度为7.5×10 15 cm -3以下，迁移率为15cm 2 / Vs以上。

公开(公告)号：US09502246B2

公开(公告)日：2016-11-22

申请号：US14455805

申请日：2014-08-08

Applicant: Samsung Display Co., Ltd. ,  University-Industry Foundation (UIF), Yonsei University

Inventor： Yeon-Hong Kim ,  Byung-Du Ahn ,  Hyeon-Sik Kim ,  Yeon-Gon Mo ,  Ji-Hun Lim ,  Hyun-Jae Kim

IPC: H01L21/02

CPC classification number: H01L21/02664 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L2227/323

Abstract: A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided. An oxide semiconductor device may be formed over the first major surface to provide an intermediate device, and the semiconductor device may comprise an oxide active layer. The intermediate device may be subjected to ultraviolet (UV) light (e.g., ultraviolet ray irradiation process) for a first period, and subjected to heat (e.g., thermal treatment process) for a second period. The first and second periods may at least partly overlap.

Abstract translation: 可以提供形成氧化物半导体器件的方法。 在该方法中，可以提供包括第一主表面和远离第一主表面的第二主表面的基板。 可以在第一主表面上形成氧化物半导体器件以提供中间器件，并且半导体器件可以包括氧化物有源层。 中间装置可以经受第一阶段的紫外线（UV）光（例如紫外线照射处理），并进行第二时段的加热（例如热处理）。 第一和第二周期可以至少部分重叠。

公开(公告)号：US10319711B2

公开(公告)日：2019-06-11

申请号：US15638961

申请日：2017-06-30

Applicant: Samsung Display Co., Ltd.

Inventor： Jung-Hyun Kim ,  Yeon-Hong Kim ,  Ki-Wan Ahn

IPC: H01L27/02 ,  H01L27/32 ,  H01L27/12

Abstract: An organic light emitting display device includes a substrate including a pixel region and a peripheral region, a first wiring, a second wiring, a third wiring, and an electrostatic protection structure including electrostatic protection diodes coupled to the first, second, and third wirings. The electrostatic protection diodes each include an active pattern, a gate electrode pattern, and a connection pattern. The active pattern is at the peripheral region of the substrate, and has a first region, a second region spaced apart from the first region, and a third region between the first and second regions. The gate electrode pattern is at the third region on the active pattern. The connection pattern is coupled to the gate electrode pattern and the active pattern and is on the gate electrode pattern, and overlaps a portion of the first region of the active pattern and a portion of the third region.