Abstract:
A driving circuit includes a receiver configured to receive an image control signal comprising a data signal and a clock signal, separate the data signal from the clock signal and output the separated data and clock signals, a clock recovery unit generating a reference clock signal based on the clock signal and generating a plurality of multi-phase clock signals having different phases from that of the reference clock signal, an output clock generation unit outputting an output clock signal in synchronization with the clock signal and the plurality of multi-phase clock signals, and a data output unit driving a plurality of data lines with a data driving signal corresponding to the data signal in synchronization with the output clock signal, and the output clock generation unit outputs the plurality of multi-phase clock signals.
Abstract:
Disclosed is a display apparatus including: a display panel including pixels connected with a plurality of gate lines and a plurality of data lines; a gate driver supplying gate signals to the gate lines; and a data driver supplying data voltages to the data lines. The data driver includes a temperature measurer generating a temperature signal of the data driver.
Abstract:
A display substrate includes a first conductive line extending along a first direction and a second conductive line partially overlapping the first conductive line with a first insulation layer in between. The second conductive line includes a first substantially linear portion and a second substantially linear portion extending along the first direction, and an angled portion disposed between the first substantially linear portion and the second substantially linear portion. At least one side surface of the angled portion extends along a second direction intersecting the first direction.
Abstract:
There is provided a display device including a power management integrated circuit outputting a driving voltage and a gamma voltage, a timing controller outputting an image data signal and a driving control signal, a data driver converting the image data signal to a data voltage signal based on the driving voltage, the gamma voltage, and the driving control signal, a power connecting portion connecting the power management integrated circuit and the data driver, a voltage detector detecting the driving voltage and the gamma voltage that are voltage-dropped in the power connecting portion, and outputting a feedback signal, and a power adjustor receiving the feedback signal and outputting a power control signal to the power management integrated circuit, and adjusting the driving voltage and the gamma voltage based on the power control signal.
Abstract:
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
Abstract:
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
Abstract:
A pixel of an organic light emitting display device includes a transistor, an organic light emitting diode, and a common line. The organic light emitting diode includes a first common layer, an organic light emitting layer disposed on the first common layer, and a second common layer. The common line is disposed between the first common layer and the second common layer to make electrical contact with the first common layer. The common line is supplied with a reference voltage to prevent the organic light emitting diode from generating light by leakage current in the transistor.