公开(公告)号：US08848152B2

公开(公告)日：2014-09-30

申请号：US13924081

申请日：2013-06-21

Applicant: Samsung Display Co., Ltd.

Inventor： Seon-Kyoon Mok ,  Si-Hyun Ahn ,  Woo-Jung Shin ,  Byoung-Sun Na ,  So-Young Kim

IPC: G02F1/1345 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/133

CPC classification number: G02F1/136286 ,  G02F1/133 ,  G02F1/1345 ,  G09G3/3696

Abstract: A display substrate includes a plurality of gate lines extending in a first direction and arranged in a second direction in a display area of the display substrate, an alignment film formed in the display area and in an end area adjacent to end portions of the gate lines in a peripheral area surrounding the display area, and a plurality of circuit stages formed in the end area to connect to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages. Each of the circuit stages includes a gate driving circuit disposed at the higher portion the gate line corresponding to the circuit stages and a gate connecting line formed in the peripheral area between the display area and the gate driving circuit to connect each of the circuit stages with each of the gate lines.

Abstract translation: 显示基板包括在显示基板的显示区域中沿第一方向延伸并沿第二方向布置的多条栅极线，形成在显示区域中的取向膜和与栅极线的端部相邻的端部区域 在围绕显示区域的外围区域中，以及形成在端部区域中以连接到栅极线的多个电路级以及连接到电路级的最后电路级的虚拟级。 每个电路级包括设置在对应于电路级的栅极线的较高部分处的栅极驱动电路和形成在显示区域和栅极驱动电路之间的周边区域中的栅极连接线，以将每个电路级与每个电路级连接 每条门线。

公开(公告)号：US09729146B2

公开(公告)日：2017-08-08

申请号：US14581423

申请日：2014-12-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Si-Hyun Ahn ,  Seung-Soo Baek ,  Byoung-Sun Na ,  Noboru Takeuchi

IPC: G09G3/36 ,  G11C19/28 ,  H03K17/693 ,  H03K17/284 ,  H03K17/687 ,  G09G3/20

CPC classification number: H03K17/693 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28 ,  H03K17/284 ,  H03K17/6874

Abstract: A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.